CEP09N7A/CEB09N7A
CEF09N7A
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Dynamic Characteristics
c
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 700V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
GS
= -30V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 5A
2
Min
700
50
100
-100
4
1.2
Typ
Max
Units
V
µA
4
nA
nA
V
Ω
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
g
V
SD
V
DS
= 5V, I
D
= 8A
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
8
1800
160
17
20
40
14
76
14
42.5
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
8
A
V
V
DD
= 300V, I
D
= 8A,
V
GS
= 10V, R
GEN
= 10Ω
7
38
7
32
10
9
V
DS
= 480V, I
D
= 8A,
V
GS
= 10V
Drain-Source Diode Characteristics and Maximun Ratings
V
GS
= 0V, I
S
= 8A
1.6
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
e.Limited only by maximum temperature allowed .
f .Pulse width limited by safe operating area .
g.Full package I
S(max)
= 4.3A .
2
FPGA/CPLD
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