FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers
October 2003
Revised March 2005
FIN1217 • FIN1218 •
FIN1215 • FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and trans-
mitted.
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and De-
serializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s
Low power consumption
s
20 MHz to 85 MHz shift clock support
s
50% duty cycle on the clock output of receiver
s
r
1V common-mode range around 1.2V
s
Narrow bus reduces cable size and cost
s
High throughput (up to 1.785 Gbps throughput)
s
Up to 595 Mbps per channel
s
Internal PLL with no external component
s
Compatible with TIA/EIA-644 specification
s
Devices are offered in 48-lead TSSOP packages
Ordering Code:
Order Number
FIN1215MTD
FIN1215MTDX_NL
(Note 1)
FIN1216MTD
FIN1216MTDX_NL
(Note 1)
FIN1217MTD
FIN1218MTD
Package
Number
MTD48
MTD48
MTD48
MTD48
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm
Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm
Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500876
www.fairchildsemi.com
FIN1217 • FIN1218 • FIN1215 • FIN1216
Transmitters
Pin Descriptions
Pin Names
TxIn
TxCLKIn
TxOut
TxOut
TxCLKOut
TxCLKOut
PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
I/O Type Number of Pins
I
I
O
O
O
O
I
I
I
I
I
I
I
21
1
3
3
1
1
1
1
2
1
3
4
5
Description of Signals
LVTTL Level Inputs
LVTTL Level Clock Input
The rising edge is for data strobe.
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in high-impedance state.
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Outputs
Ground Pins for LVDS Outputs
Power Supply Pins for LVTTL Inputs
Ground pins for LVTTL Inputs
No Connect
Connection Diagram
FIN1217 and FIN1215 (21:3 Transmitter)
Pin Assignment for TSSOP
3
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FIN1217 • FIN1218 • FIN1215 • FIN1216
Receivers
Pin Descriptions
Pin Names
RxIn
RxIn
RxCLKIn
RxCLKIn
RxOut
RxCLKOut
PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
I/O Type
I
I
I
I
O
O
I
I
I
I
I
I
I
Number
of
Pins
3
3
1
1
21
1
1
1
2
1
3
4
5
Description of Signals
Negative LVDS Differential Data Inputs
Positive LVDS Differential Data Inputs
Negative LVDS Differential Clock Input
Positive LVDS Differential Clock Input
LVTTL Level Data Outputs
Goes HIGH for PwrDn LOW
LVTTL Clock Output
LVTTL Level Input
Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Inputs
Ground Pins for LVDS Inputs
Power Supply for LVTTL Outputs
Ground Pins for LVTTL Outputs
No Connect
Connection Diagram
FIN1218 and FIN1216 (3:21 Receiver)
Pin Assignment for TSSOP
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4
FIN1217 • FIN1218 • FIN1215 • FIN1216
Truth Tables
Transmitter Truth Table
Inputs
TxIn
Active
Active
F
F
X
H HIGH Logic Level
L LOW Logic Level
X Don’t Care
Z High Impedance
F Floating
Note 2:
The outputs of the transmitter or receiver will remain in a High Impedance state until V
CC
reaches 2V.
Note 3:
TxCLKOut
r
will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z).
Outputs
PwrDn (Note 2)
H
H
H
H
L
TxOut
r
L/H
L/H
L
L
Z
TxCLKOut
r
L/H
X (Note 3)
L/H
X (Note 3)
Z
TxCLKIn
Active
L/H/Z
Active
F
X
Receiver Truth Table
Inputs
RxIn
r
Active
Active
F (Note 5)
F (Note 5)
X
H HIGH Logic Level
L LOW Logic Level
P Last Valid State
X Don’t Care
Z High Impedance
F Failsafe Condition
Note 4:
The outputs of the transmitter or receiver will remain in a High Impedance state until V
CC
reaches 2V.
Note 5:
Failsafe condition is defined as the input being terminated and un-driven (Z) or shorted or open.
Note 6:
If RxCLKIn
r
is removed prior to the RxIn
r
data being removed, RxOut will be the last valid state. If RxIn
r
data is removed prior to RxCLKIn
r
being
removed, RxOut will be HIGH.
Outputs
PwrDn (Note 4)
H
H
H
H
L
RxOut
L/H
P
H
P (Note 6)
L
RxCLKOut
L/H
H
L/H
H
H
RxCLKIn
r
Active
F (Note 5)
Active
F (Note 5)
X
5
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