3968
A3968SLB
(SOIC)
OUT
1A
INPUT
1A
INPUT
1B
GROUND
SENSE
1
OUT
1B
LOAD
SUPPLY
REFERENCE
1
2
3
4
5
6
7
8
V
REF
V
BB
V
CC
RC
LOGIC
LOGIC
V
BB
16
15
14
13
12
11
10
9
OUT
2A
INPUT
2A
INPUT
2B
GROUND
SENSE
2
OUT
2B
LOGIC
SUPPLY
RC
DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
The A3968SA and A3968SLB are designed to bidirectionally control two
dc motors. Each device includes two H-bridges capable of continuous output
currents of ±650 mA and operating voltages to 30 V. Motor winding current
can be controlled by the internal fixed-frequency, pulse-width modulated
(PWM), current-control circuitry. The peak load current limit is set by the
user’s selection of a reference voltage and current-sensing resistors. Except
for package style and pinout, the two devices are identical.
The fixed-frequency pulse duration is set by a user-selected external RC
timing network. The capacitor in the RC timing network also determines a
user-selectable blanking window that prevents false triggering of the PWM
current-control circuitry during switching transitions.
To reduce on-chip power dissipation, the H-bridge power outputs have
been optimized for low saturation voltages. The sink drivers feature the
Allegro
®
patented Satlington
®
output structure. The Satlington outputs
combine the low voltage drop of a saturated transistor and the high peak
current capability of a Darlington.
For each bridge, the INPUT
A
and INPUT
B
terminals determine the load
current polarity by enabling the appropriate source and sink driver pair. When
a logic low is applied to both INPUTs of a bridge, the braking function is
enabled. In brake mode, both source drivers are turned OFF and both sink
drivers are turned ON, thereby dynamically braking the motor. When a logic
high is applied to both INPUTs of a bridge, all output drivers are disabled.
Special power-up sequencing is not required. Internal circuit protection
includes thermal shutdown with hysteresis, ground-clamp and flyback diodes,
and crossover-current protection.
The A3968SA is supplied in a 16-pin dual in-line plastic package. The
A3968SLB is supplied in a 16-pin plastic SOIC with copper heat sink tabs.
The power tab is at ground potential and needs no electrical isolation. The LB
package is available in a lead (Pb) free version (100% matte tin leadframe).
Data Sheet
29319.29E
Dwg. PP-066
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
...................
30 V
Output Current, I
OUT
(peak) ..........
±750 mA
(continuous) ..............................
±650 mA
Logic Supply Voltage, V
CC
.................
7.0 V
Input Voltage, V
in
.....
-0.3 V to V
CC
+ 0.3 V
Sense Voltage, V
S
................................
1.0 V
Package Power Dissipation (T
A
= 25°C), P
D
A3968SA .....................................
1.8 W*
A3968SLB ...................................
1.4 W*
Operating Temperature Range,
T
A
...................................
-20°C to +85°C
Junction Temperature,
T
J
.................................................
+150°C
Storage Temperature Range,
T
S
.................................
-55°C to +150°C
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
* Per SEMI G42-88 Specification,
Thermal Test
Board Standardization for Measuring Junction-
to-Ambient Thermal Resistance of Semiconductor
Packages.
FEATURES
■
■
■
■
■
■
■
■
■
±650 mA Continuous Output Current
30 V Output Voltage Rating
Internal Fixed-Frequency PWM Current Control
Satlington Sink Drivers
Brake Mode
User-Selectable Blanking Window
Internal Ground-Clamp & Flyback Diodes
Internal Thermal-Shutdown Circuitry
Crossover-Current Protection and UVLO Protection
Part Number
A3968SLB-T
A3968SLBTR-T
*
Pb-free*
Yes
Yes
R
θJA
(°C/W)
90
90
R
θJT
(°C/W)
6
6
Package
16-Lead SOIC
16-Lead SOIC
Packing
47 per tube
1000 per reel
Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be LAST TIME BUY. This
classification indicates that sale of this device is currently restricted to existing customer
applications. The variants should not be purchased for new design applications because
obsolescence in the near future is probable. Samples are no longer available. Status
change: October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007.
These variants include: A3968SA, A3968SLB, and A3968SLBTR.
3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL DESCRIPTION
Internal PWM Current Control.
The A3968SA and
A3968SLB dual H-bridges are designed to bidirectionally
control two dc motors. An internal fixed-frequency PWM
current-control circuit controls the load current in each
motor. The current-control circuitry works as follows:
when the outputs of the H-bridge are turned on, current
increases in the motor winding. The load current is sensed
by the current-control comparator via an external sense
resistor (R
S
). Load current continues to increase until it
reaches the predetermined value, set by the selection of
external current-sensing resistors and reference input
voltage (V
REF
) according to the equation:
I
TRIP
= I
OUT
+ I
SO
= V
REF
/(4R
S
)
where I
SO
is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-
enable latch, turning off the source driver of that H-bridge.
The source turn off of one H-bridge is independent of the
other H-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp
diode. The current decreases until the internal clock
oscillator sets the source-enable latches of both H-bridges,
turning on the source drivers of both bridges. Load current
increases again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components R
T
C
T
. The frequency
can be approximately calculated as:
f
osc
= 1/(R
T
C
T
+ t
blank
)
where t
blank
is defined below.
The range of recommended values for R
T
and C
T
are
20 kΩ to 100 kΩ and 470 pF to 1000 pF respectively.
Nominal values of 56 kΩ and 680 pF result in a clock
frequency of 25.4 kHz.
Current-Sense Comparator Blanking.
When the
source driver is turned on, a current spike occurs due to
the reverse-recovery currents of the clamp diodes and
switching transients related to distributed capacitance in
the load. To prevent this current spike from erroneously
resetting the source enable latch, the current-control
comparator output is blanked for a short period of time
when the source driver is turned on. The blanking time is
set by the timing component C
T
according to the equa-
tion:
t
blank
= 1900 C
T
(µs).
A nominal C
T
value of 680 pF will give a blanking
time of 1.3 µs.
The current-control comparator is also blanked when
the load current changes polarity (direction or phase
change). This internally generated blank time is approxi-
mately 1.8 µs.
V
V
PHASE
BB
See Enlargement A
+
I
OUT
0
–
BRIDGE
ON
ALL
OFF
BRIDGE ON
SOURCE OFF
ALL OFF
BRIDGE
ON
Enlargement A
t
d
I
TRIP
SOURCE
OFF
t
blank
INTERNAL
OSCILLATOR
R
T
C
T
Dwg. WM-003-2
RS
Dwg. EP-006-16
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