NIS5112
Electronic Fuse
The NIS5112 is an integrated switch utilizing a high side N−channel
FET driven by an internal charge pump. This switch features a
MOSFET which allows for current sensing using inexpensive chip
resistors instead of expensive, low impedance current shunts.
It is designed to operate in 12 V systems and includes a robust
thermal protection circuit.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8 NB
CASE 751
1
x
112x
AYWWG
G
•
•
•
•
•
•
•
•
•
•
Integrated Power Device
Power Device Thermally Protected
No External Current Shunt Required
Enable/Timer Pin
Adjustable Slew Rate for Output Voltage
9 V to 18 V Input Range
30 mW Typical
Internal Charge Pump
ESD Ratings: Human Body Model (HBM); 4000 V
These are Pb−Free Devices
Typical Applications
= L for thermal latch off
= H for thermal auto−retry
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
Hard Drives
ORDERING INFORMATION
Device
NIS5112D1R2G
Package
SOIC−8
Latch Off
(Pb−Free)
SOIC−8
Auto−Retry
(Pb−Free)
Shipping
†
2500
Tape & Reel
2500 /
Tape & Reel
8
V
CC
NIS5112D2R2G
Voltage
Regulator
Charge
Pump
Current
Limit
Overvoltage
Clamp
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Current Limit
4
Thermal
Latch
Voltage
Slew Rate
Source
5, 6, 7
Enable/
Timer
Enable/Timer
3
GND
1
dV/dt
2
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2011
April, 2017
−
Rev. 10
1
Publication Order Number:
NIS5112/D
NIS5112
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
3
1
4
5,6,7
2
8
Function
Enable/Timer
Ground
I
Limit
Source
dV/dt
V
CC
Description
A high level signal on this pin allows the device to begin operation. Connection of a capacitor will delay
turn on for timing purposes. A low input signal inhibits the operation.
Negative input voltage to the device. This is used as the internal reference for the IC.
A resistor between this pin and the source pin sets the current limit level.
Source of power FET, which is also the switching node for the load.
A capacitor from this pin to ground programs the slew rate of the output at turn on. This capacitor is
discharged by an internal discharge circuit when the device is disabled via the enable pin.
Positive input voltage to the device.
Table 2. MAXIMUM RATINGS
(Maximum ratings are those, that, if exceeded, may cause damage to the device. Electrical
characteristics are not guaranteed over this range)
Rating
Input Voltage, Operating,
Drain Voltage, Operating,
Drain Current, Peak (Internally Clamped)
Drain Current, Continuous (T
A
=25°C), (Note 2)
Thermal Resistance, Junction−to−Air
0.5 in
2
Copper
1.0 in
2
Copper
Thermal Resistance, Junction−to−Lead (Pin 8)
Power Dissipation (T
A
= 25°C) (Note 1)
Operating Temperature Range (Note 2)
Nonoperating Temperature Range
Lead Temperature, Soldering (10 Sec)
Steady−State (Input+ to Input−)
Transient (Conditions 1 ms)
Steady−State (Drain to Input−)
Transient (Conditions 1 ms)
Symbol
V
in
V
DD
I
Dpk
I
Davg
Q
JA
Value
−0.3
to 18
−0.3
to 25
−0.3
to 18
−0.3
to 25
25
5.3
120
110
27
1.0
−40
to 175
−55
to 175
260
Unit
V
V
A
A
°C/W
°C/W
°C/W
W
°C
°C
°C
Q
JL
P
max
T
J
T
J
T
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on FR−4 board, 1 in sq pad, 1 oz coverage.
2. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as
specified.
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2
NIS5112
Table 3. ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V
CC
= 12 V, R
LIMIT
= 56
W
T
J
= 25°C)
Characteristics
POWER FET
Delay Time (Enabling of Chip to Beginning of Conduction (10% of IPK))
Charging Time (Beginning of Conduction to 90% of V
out
)
C
dV/dt
= 1
mF,
C
load
= 1000
mF
ON Resistance
(I
D
= 2 A, T
J
=
−20°C)
(Note 3)
(I
D
= 2 A, T
J
= 25°C)
(I
D
= 2 A, T
J
= 100°C) (Note 3)
Off State Output Voltage
(V
in
= 12 V
dc
, Enable Low, V
dc
, T
J
=
−20°C)
(Note 3)
(V
in
= 12 V
dc
, Enable Low, T
J
= 25°C)
(V
in
= 12 V
dc
, Enable Low, T
J
= 100°C) (Note 3)
Output Capacitance (V
DS
= 12 V
dc
, V
GS
= 0 V
dc
, f = 10 kHz)
THERMAL LATCH
Shutdown Temperature (Note 3)
Thermal Hysteresis (Auto Retry Only) (Note 3)
ENABLE/TIMER
Enable Voltage (Turn−on)
(R
load
= 2 K, T
J
=
−20°C)
(Note 3)
(R
load
= 2 K, T
J
= 25°C)
(R
load
= 2 K, T
J
= 100°C) (Note 3)
Enable Voltage (Turn−off)
(R
load
= 2 K, T
J
=
−20°C)
(Note 3)
(R
load
= 2 K, T
J
= 25°C)
(R
load
= 2 K, T
J
= 100°C) (Note 3)
Charging Current (Current Sourced into Timing Cap)
(T
J
=
−20°C)
(Note 3)
(T
J
= 25°C)
(T
J
= 100°C) (Note 3)
OVERVOLTAGE CLAMP
Output Clamping Voltage
(V
CC
= 18 V, T
J
=
−20°C)
(Note 3)
(V
CC
= 18 V, T
J
= 25°C)
(V
CC
= 18 V, T
J
= 100°C) (Note 3)
CURRENT LIMIT
Short Circuit Current Limit,
(R
extILimit
= 56
W,
T
J
=
−20°C)
(Note 3)
(R
extILimit
= 56
W,
T
J
= 25°C)
(R
extILimit
= 56
W,
T
J
= 100°C) (Note 3)
Overload Current Limit, (Note 3)
(R
extILimit
= 56
W,
T
J
=
−20°C)
(R
extILimit
= 56
W,
T
J
= 25°C)
(R
extILimit
= 56
W,
T
J
= 100°C)
dV/dt CIRCUIT
Slew Rate
(C
dV/dt
= 1
mf)
Charging Current (Current Sourced into dV/dt Cap)
(T
J
=
−20°C)
(Note 3)
(T
J
= 25°C)
(T
J
= 100°C) (Note 3)
Max Capacitor Voltage
TOTAL DEVICE
Bias Current (Device Operational, Load Open, V
in
= 12 V)
Minimum Operating Voltage
3. Verified by design.
I
Bias
V
min
−
−
1.45
−
2.0
9.0
mA
V
dV/dt
I
dV/dt
0.130
67
70
71
−
0.15
80
83
84
−
0.170
90
92
96
V
CC
V/ms
mA
I
Lim−SS
2.05
2.0
1.7
3.7
3.5
3.4
2.7
2.5
2.3
4.6
4.4
4.3
3.2
3.0
2.7
5.5
5.3
5.2
A
V
Clamp
14
14
13
15.5
15
14.5
17
16.2
16
V
V
ENon
2.45
2.5
2.7
−
−
−
67
70
71
−
−
−
−
−
−
80
83
84
−
−
−
1.8
1.9
2.0
90
92
96
V
T
SD
T
hyst
125
−
135
40
145
−
°C
°C
T
dly
t
chg
R
DSon
−
−
−
5.0
64
−
−
ms
ms
mW
Symbol
Min
Typ
Max
Unit
23.5
28
37
−
−
−
396
27.5
32
43.5
120
120
200
−
V
off
−
−
−
−
mV
pF
V
ENoff
V
I
Charge
mA
I
Lim−OL
A
V
max
V
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3
NIS5112
100
140
120
10
I
Limit
(A)
I
LIMIT
_OL
100
POWER (W)
80
60
40
I
LIMIT
_SS
0
10
100
R
extILimit
(W)
1000
20
0
1
10
100
TIME (ms)
1000
10000
T
A
= 25°C
1/2 in
2
, 1 oz copper,
double sided board
1
Figure 2. Current Limit Adjustment
Figure 3. Overload vs. Shutdown Time
+12 V
Source
56
W
Current Limit
NIS5112
Enable signal is compatible
with open collector devices
as well as most families.
Enable/
Timer GND
dV/dt
1
mF
Load
Enable
GND
(Typical operating conditions: V
in
= 12 V, R
ILimit
= 56
W,
C
dV/dt
= 1
mF)
Figure 4. Typical Application Circuit
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NIS5112
Input Voltage
Output Voltage
Slew Rate = 0.14 V/ms
Load Current
Figure 5. Turn−on Waveforms for a Resistive Load of 10
W
(C
dV
/
dt
= 1
mf)
Input Voltage
Output Voltage
Slew Rate = 0.14 V/ms
Load Current (i = C dV/dt)
Figure 6. Turn−on Waveforms for a Load Capacitance of 3,300
mf
(C
dV
/
dt
= 1
mf)
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Microchip MCU
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