NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
The NB100LVEP224 is a low skew 1-to-24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low output-to-output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive V
CC
supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single-ended CLK input operation is
limited to a V
CC
≥
3.0 V in LVPECL mode, or V
EE
≤
-3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
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MARKING
DIAGRAM*
64
1
64
1
NB100
LVEP224
AWLYYWW
64-LEAD LQFP
CASE 848G
THERMALLY ENHANCED
FA SUFFIX
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP224FA
Package
LQFP-64
Shipping
160 Units/Tray
•
•
•
•
•
NB100LVEP224FAR2 LQFP-64 1500/Tape & Reel
20 ps Typical Output-to-Output Skew
75 ps Typical Device-to- Device Skew
Maximum Frequency > 1 GHz
650 ps Typical Propagation Delay
LVPECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= -2.375 V to -3.8 V
•
Internal Input Pulldown Resistors
•
Q Output will Default Low with Inputs Open or at V
EE
•
Thermally Enhanced 64-Lead LQFP
•
CLOCK Inputs are LVDS-Compatible; Requires External 100
W
LVDS Termination Resistor
©
Semiconductor Components Industries, LLC, 2003
1
June, 2003 - Rev. 4
Publication Order Number:
NB100LVEP224/D
NB100LVEP224
Q10
Q10
Q12
Q12
Q13
Q13
Q14
Q14
34
Q11
Q11
V
EE
V
CCO
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
V
CCO
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
47
46
45
44
43
42
41
40
39
38
37
36
35
V
EE
33
32
31
30
29
28
27
26
25
V
CCO
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
Q21
Q21
V
CCO
24
23
22
21
20
19
18
17
15
16
Q0-Q23
CLK0
CLK1
L
L
V
CCO
Q22
Q8
Q8
Q9
Q9
NB100LVEP224
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK0
Q23
V
CCO
CLK1
CLK_SEL
CLK0
CLK1
Q23
Q0
Q0
V
CC
All V
CC
, V
CCO
, and V
EE
pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to V
EE
internally.
Figure 1. 64-Lead LQFP Pinout
(Top View)
PIN DESCRIPTION
PIN
CLK0*, CLK0**
CLK1*, CLK1**
CLK_SEL*
OE*
Q0-Q23, Q0-Q23
V
CC
, V
CCO
V
EE
***
FUNCTION
ECL Differential Input Clock
ECL Differential Input Clock
ECL Input CLK Select
ECL Output Enable
ECL Differential Outputs
Positive Supply
Negative Supply
FUNCTION TABLE
OE (1)
L
L
H
H
CLK_SEL
L
H
L
H
Q0-Q23
CLK0
CLK1
H
H
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to V
EE
internally.
1. The OE (Output Enable) signal is synchronized with the
falling edge of the LVPECL_CLK signal.
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2
Q22
V
EE
OE
NB100LVEP224
CLK_SEL
CLK0
CLK0
CLK1
CLK1
V
CC
V
EE
0
24
24
1
Q
OE
D
Q0-Q23
Q0-Q23
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
37.5 kW
> 2 kV
> 150 V
> 2 kV
Level 3
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
654 Devices
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
EE
V
I
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
(See Application Information)
Thermal Resistance (Junction-to-Case)
(See Application Information)
Wave Solder
0 LFPM
500 LFPM
0 LFPM
500 LFPM
< 2 to 3 sec @ 248°C
64 LQFP
64 LQFP
64 LQFP
64 LQFP
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
6
-6
6 to 0
-6 to 0
0 to +85
-65 to +150
35.6
30
3.2
6.4
265
Units
V
V
V
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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NB100LVEP224
LVPECL DC CHARACTERISTICS
V
CC
= 2.5 V; V
EE
= 0 V (Note 3)
-40
°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single-Ended)
(Note 9)
Input LOW Voltage (Single-Ended)
(Note 9)
Input HIGH Voltage Common Mode
Range (Differential) (Note 10)
CLK/CLK
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
-150
Min
130
1355
555
1335
555
Typ
160
1480
680
Max
195
1605
900
1620
900
Min
135
1355
555
1335
555
25°C
Typ
165
1480
680
Max
200
1605
900
1620
900
Min
140
1355
555
1275
555
85°C
Typ
165
1480
680
Max
205
1605
900
1620
900
Unit
mA
mV
mV
mV
mV
1.2
2.5
150
1.2
2.5
150
1.2
2.5
150
V
mA
mA
I
IH
I
IL
NOTE:
3.
4.
5.
6.
0.5
-150
0.5
-150
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is
maintained.
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary + 0.125 V to -1.3 V.
All outputs loaded with 50
W
to V
CC
- 2.0 V.
Do not use V
BB
at VCC < 3.0 V.
V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differen-
tial input signal.
LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0 V (Note 7)
-40
°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single-Ended)
(Note 9)
Input LOW Voltage (Single-Ended)
(Note 9)
Input HIGH Voltage Common Mode
Range (Differential) (Note 10) (Figure
5)
Input HIGH Current
Input LOW Current
CLK
CLK
0.5
-150
Min
140
2155
1355
2135
1355
1.2
Typ
165
2280
1480
Max
195
2405
1700
2420
1700
3.3
Min
145
2155
1355
2135
1355
1.2
25°C
Typ
175
2280
1480
Max
205
2405
1700
2420
1700
3.3
Min
145
2155
1355
2135
1355
1.2
85°C
Typ
175
2280
1480
Max
210
2405
1700
2420
1700
3.3
Unit
mA
mV
mV
mV
mV
V
I
IH
I
IL
NOTE:
150
0.5
-150
150
0.5
-150
150
mA
mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to -0.5 V.
8. All outputs loaded with 50
W
to V
CC
- 2.0 V.
9. Single ended input operation is limited V
CC
≥
3.0 V in LVPECL mode.
10. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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4
NB100LVEP224
NECL DC CHARACTERISTICS
V
CC
= 0 V, V
EE
= -2.375 V to -3.8 V (Note 11)
-40
°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
V
EE
= -2.5 V
V
EE
= -3.3 V
Min
130
140
-1 145
-1945
-1 165
-1945
V
EE
+ 1.2
Typ
160
165
-1020
-1820
Max
195
195
-895
-1600
-880
-1600
0.0
Min
135
145
-1 145
-1945
-1 165
-1945
V
EE
+ 1.2
25°C
Typ
165
175
-1020
-1820
Max
200
205
-895
-1600
-880
-1600
0.0
Min
140
145
-1 145
-1945
-1 165
-1945
V
EE
+ 1.2
85°C
Typ
165
175
-1020
-1820
Max
205
210
-895
-1600
-880
-1600
0.0
Unit
mA
mV
mV
mV
mV
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single-Ended)
(Note 13)
Input LOW Voltage (Single-Ended)
(Note 13)
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
(Figure 5)
Input HIGH Current
Input LOW Current
CLK
CLK
I
IH
I
IL
NOTE:
150
0.5
-150
0.5
-150
150
0.5
-150
150
mA
mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with V
CC
.
12. All outputs loaded with 50
W
to V
CC
- 2.0 V.
13. Single ended input operation is limited V
EE
≤
-3.0 V in NECL mode.
14. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS
V
CC
= 2.375 V to 3.8 V; V
EE
= 0 V (Note 15)
-40
5C
Symbol
V
Opp
Characteristic
Differential Output Voltage
(Figure 3)
f
out
< 50 MHz
f
out
< 0.8 GHz
f
out
< 1.0 GHz
CLKx-Qx
CLK_SELx-Qx
Within-Device Skew (Note 16)
Device-to-Device Skew (Note 17)
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential) (Note 19) (Figure 5)
OE Set Up Time (Note 18)
OE Hold Time
Output Rise/Fall Time
(20%-80%)
200
200
200
100
200
300
Min
600
600
600
500
600
Typ
750
750
700
600
700
20
50
1
800
700
800
40
300
5
1200
200
200
200
100
200
300
Max
Min
600
600
525
550
650
255C
Typ
725
725
650
650
800
20
50
1
800
750
900
40
300
5
1200
200
200
200
150
250
350
Max
Min
575
550
400
650
750
855C
Typ
700
650
525
750
850
35
100
1
800
1000
1150
60
300
5
1200
Max
Unit
mV
mV
mV
ps
ps
ps
ps
ps
mV
ps
ps
ps
t
PLH
t
PHL
t
skew
t
JITTER
V
PP
t
S
t
H
t
r
/t
f
Propagation Delay (Differential)
15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50
W
to V
CC
- 2 V.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions at identical V
CC
levels.
18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High-to-Low transition ensures outputs remain disabled during
the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock.
19. V
PP
is the differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
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