Integrated
Circuit
Systems, Inc.
ICS94228
Programmable System Clock Chip for AMD - K7™ processor
Recommended Application:
VIA KT266 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks @ 2.7V
•
1 - Differential pair push-pull CPU clocks @ 2.5V
•
11 - PCI including 1 free running and 1 early @ 3.3V
•
1 - 48MHz, @ 3.3V fixed
•
1 - 24/48MHz @ 3.3V
•
3 - REF @ 3.3V, 14.318MHz.
Features:
•
Programmable output frequency.
•
Programmable output rise/fall time.
•
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
•
Real time system reset output.
•
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
Skew Specifications:
•
CPU - CPU: <200ps
•
PCI - PCI: <500ps
•
CPU (early - PCI: min=1.0ns, max=2.6ns
•
CPU cycle to cycle jitter: <250ps
Pin Configuration
VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
Functionality
48MHz (1:0)
24_48MHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
REF (1:0)
REF_F
CPU
DIVDER
Stop
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
PCICLK9_E
CPU
DIVDER
Stop
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
REF_STOP#
0447E—05/07/04
Control
Logic
PCI
DIVDER
Stop
9
PCICLK (8:0)
PCICLK_F
AGP
DIVDER
Stop
3
AGP (2:0)
Config.
Reg.
SRESET#
CPU
(MHz)
233.33
220.00
210.00
200.00
190.00
180.00
170.00
150.00
140.00
120.00
110.00
66.67
200.00
166.67
100.00
133.33
ICS94228
AG P
(MHz)
77.78
73.33
70.00
66.67
76.00
72.00
68.00
75.00
70.00
60.00
66.00
66.67
66.67
66.67
66.67
66.67
PCICLK
(MHz)
38.88
36.67
35.00
33.33
38.00
36.00
34.00
37.50
35.00
30.00
33.00
33.33
33.33
33.33
33.33
33.33
ICS94228
Pin Descriptions
PIN NUMBER
1, 15, 23, 25,
2, 8, 12, 19,
29, 37, 43
3
4
5
6
7
9
10
21, 20, 18, 17,
16, 14, 13, 11
22
24
28, 27, 26
30
31
32
33
34
35
36
38
39
40
42
41
44
45
46
47
48
PIN NAME
VDD
GND
X1
X2
AVDD48
FS2
1, 2
48MHz
FS3
1, 2
24_48MHz
PCICLK_F
SEL24_48#
1, 2
PCICLK0
PCICLK (8:1)
PCICLK9_E
SRESET#
1
AGP (2:0)
SCLK
SDATA
AGND
AVDD
PD#
PCI_STOP#
CPU_STOP#
1, 2
CPUCLK_CSC0
CPUCLK_CST0
VDDL
CPUCLKT0
CPUCLKC0
AGP_STOP#
REF_STOP#
REF_F
FS1
FS0
1, 2
TYPE
P W R Power supply, nominal 3.3V
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
I/O
PWR
PWR
IN
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
Ground
DESCRIPTION
Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF)
Power supply, nominal 3.3V
Frequency select pin. Latched Input
48MHz output clock, stoppable by REF_Stop
Frequency select pin. Latched Input
24 or 48MHz clock output, stoppable by REF_Stop
Free running PCI clock not affected by PCI_STOP# for power management.
Logic input to select 24 or 48MHz for pin 7 output
PCI clock output
PCI clock outputs.
Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#.
Real time system reset signal for watchdog tmer timeout. This signal is active low.
AGP clock outputs
Clock input of I
2
C input, 5V tolerant input
Data pin for I
2
C circuitry 5V tolerant
Analog ground
Power supply, nominal 3.3V
Asynchronous active low input pin used to power down the device into a low
p o w e r s t a t e . T h e i n t e r n a l c l o ck s a r e d i s a b l e d a n d t h e V C O a n d t h e c r y s t a l a r e
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low
This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic
"0" level when driven low.
"Complementary" clock of differential pair output chipset (push-pull).
"True" clock of differential pair CPU output chipset (push-pull).
Power supply for CPUCLKs, nominal 2.5V
"True" clock of differential pair CPU output. These open drain outputs need an
external 1.5V pull-up (open drain).
"Complementary" clock of differential pair CPU output. These open drain outputs
need an external 1.5V pull-up (open drain).
Stops all AGP clocks at logic 0 level, when input low
Stops REF, 48MHz and 24/48MHz clocks at logic 0 level, when input low.
14.318 MHz free running reference clock., not afftected by REF_STOP#
Frequency select pin. Latched Input
14.318 MHz reference clock.
Frequency select pin. Latched Input
14.318 MHz reference clock.
REF1
1, 2
REF0
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0447E—05/07/04
2
ICS94228
General Description
The
ICS94228
is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The
ICS94228
belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94228 system clock generator is a real time active low pulse that can be used to reset
the system.
The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When
activated, the SRESET# output will be driven to a low with a 32ms pulse width.
0447E—05/07/04
3
ICS94228
General I
2
C serial interface information for the ICS94228
How to Write:
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending
Byte 0 through Byte 16
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends
Byte 0 through byte 6 (default)
ICS clock sends
Byte 0 through byte X (if X
(H)
was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address D2
(H)
Dummy Command Code
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
Byte Count
ACK
Byte 0
ACK
ACK
Byte 0
Byte 1
ACK
ACK
Byte 1
Byte 2
ACK
ACK
Byte 2
Byte 3
ACK
ACK
Byte 3
Byte 4
ACK
ACK
Byte 4
Byte 5
ACK
ACK
Byte 5
Byte 6
ACK
ACK
If 7
H
has been written to B6
ACK
Byte 6
Byte 7
ACK
Byte 14
ACK
Byte 15
ACK
Byte 16
ACK
Stop Bit
If 1A
H
has been written to B6
ACK
If 1B
H
has been written to B6
ACK
If 1C
H
has been written to B6
ACK
Stop Bit
Byte 14
Byte 15
Byte 16
*See notes on the following page
.
0447E—05/07/04
4
ICS94228
Brief I
2
C registers description for ICS94228
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Output Control Registers
Byte
0
Description
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
These registers control the spread
percentage amount.
Increment or decrement the group
skew amount as compared to the
initial skew.
These registers will control the
output rise and fall time.
2
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
1, 2, 3
Vendor ID & Revision ID
Registers
5, 6, 7
Byte Count
Read Back Register
Watchdog Enable
Register
Watchdog Control
Registers
8
08
H
4
10
H
000,0000
VCO Control Selection
Bit
4, 5
0
VCO Frequency Control
Registers
9, 10
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
Spread Spectrum
Control Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
11, 12
13, 14
15, 16
Notes:
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol.
The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
2.
3.
4.
5.
6.
7.
0447E—05/07/04
5
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