Advance Data
TSC3L72T18 / 36
72 Mb Synchronous NBT 3T-iRAM™
With Low Power Core
Pipelined,
SRAM-Compatible
Features
Error-resistant 3T-iRAM™ technology
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudostatic devices to provide entirely
NBT (No Bus Turnaround) functionality for zero wait
SRAM-compatible interfaces and timing. The unique design
Read-Write-Read bus usage
Fully pin-compatible with pipelined NtRAM™, NoBL™ and of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
ZBT™
SRAMs.
1.8 V ± 0.1 V core power supply, 1.8 V or 2.5 V I/O supply
The TSC3L72T18/36 is a 72Mbit synchronous memory
LODRV pin for user-selectable drive strength
device that functions much like ZBT, NtRAM, NoBL, and
IEEE 1149.1 JTAG-compatible Boundary Scan
other pipelined read/double late write SRAMs – it exploits all
LBO
pin for Linear or Interleaved Burst mode
available bus bandwidth by eliminating “deselect cycles”
Pin-compatible with 2/4/9/18/36Mb devices
when the device is switched from read to write.
Byte write operation (9-bit Bytes)
As in all synchronous devices, address, data inputs, and
3 Chip Enable signals for easy depth expansion
read/write control inputs are captured on the rising clock
ZZ pin for automatic power-down
edge. Burst order control (
LBO
) must be tied to a power rail
JEDEC standard 165-FBGA package
for proper operation. Asynchronous inputs include the Sleep
mode enable (ZZ) and Output Enable (
G
). Output Enable
Options
Marking
can override the synchronous control of the output drivers to
Configurations: 4M x 18
TSC3L72T18
turn them off at any time. Write cycles are internally self-
2M x 36
TSC3L72T36
timed and initiated by the rising clock edge; this eliminates
the complex off-chip write pulse generation required by
Packages:
165-FBGA
B
asynchronous SRAMs and simplifies input signal timing.
Speed (MHz):
250
-250
200
166
Part number example:
TSC3L72T36B-200
-200
-166
The TSC3L72T18/36 is pipelined, with a rising-edge-
triggered output register. For read cycles, output data is
stored in the edge-triggered output register during the
access cycle and then released to the output drivers at the
next rising clock edge.
Parameter Synopsis:
tKQ
3-1-1-1
tCycle
Curr
-250
2.5
4.0
tbd
-200
3.0
5.0
tbd
-166
3.5
6.0
tbd
Unit
ns
ns
mA
Rev. 1.0 – 23 January 2007
Page 1 of 20
©2005, Tezzaron Semiconductor Corp.
Advance Data
TSC3L72T18 / 36
165-FBGA: Top View
1
2
A
A
NC
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
A
A
3
4
5
6
7
8
ADV
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQB
DQB
DQB
DQB
LODRV
DQA
DQA
DQA
DQA
NC
A
A
11
NC
NC
DQP
B
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQP
A
NC
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
x36 Common I/O:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQP
C
DQC
DQC
DQC
DQC
NC
DQD
DQD
DQD
DQD
DQP
D
NC
E1
E2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
BC
BB
BA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
E3
CK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
A0
CKE
BD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
G
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
LBO
1
2
A
A
NC
DQB
DQB
DQB
DQB
MCH
NC
NC
NC
NC
NC
A
A
3
4
5
NC
6
7
8
ADV
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
LODRV
DQA
DQA
DQA
DQA
NC
A
A
11
A
NC
DQP
A
DQA
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
NC
NC
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
x18 Common I/O:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
DQB
DQB
DQB
DQB
DQP
B
NC
E1
E2
DDQ
BB
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
E3
CK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
CKE
BA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
W
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
G
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
LBO
Rev. 1.0 – 23 January 2007
Page 2 of 20
©2005, Tezzaron Semiconductor Corp.
Advance Data
TSC3L72T18 / 36
Pin Descriptions
Symbol
A
0
, A
1
A
DQ
A
, DQ
B
,
DQ
C
, DQ
D
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset
Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os;
active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Low Drive strength control (active high)
Low = High Drive, High = Low Drive
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
Output driver power supply
BA
,
BB
,
BC
,
BD
NC
CK
CKE
W
E1
,
E3
E2
G
ADV
LODRV
ZZ
LBO
TMS
TDI
TDO
TCK
MCH
V
DD
V
SS
V
DDQ
Functional Details
Clocking
All inputs
except
Output Enable, Linear Burst Order, and Sleep are synchronized to rising clock edges. Deasserting Clock
Enable (
CKE
high) blocks the Clock input from reaching the RAM’s internal circuits, thus suspending operation. Failure to
observe Clock Enable set-up or hold requirements will result in erratic operation.
Read and Write Operations
Single cycle read and write operations are initiated with ADV held low in order to load the new address. The device is
activated by asserting all three Chip Enables (
E1
, E2
,
and
E3
). Deassertion of any Chip Enable deactivates the device.
Rev. 1.0 – 23 January 2007
Page 3 of 20
©2005, Tezzaron Semiconductor Corp.
Advance Data
TSC3L72T18 / 36
Read operation starts when the following conditions occur at a rising clock edge:
CKE
low, all three chip enables (
E1
, E2
,
and
E3
) active, write enable (
W
) high, and ADV low. The value of address inputs is latched into the address register and
presented to the memory core and control logic. The control logic determines that a read is in progress and allows the
requested data to propagate to the input of the output register. At the next rising clock edge the read data propagates
through the output register and onto the output pins.
Write operation starts when the RAM is selected,
CKE
is active, and
W
is sampled low at the rising clock edge. The Byte
Write Enables (
BA
–
BB
or
BA
–
BD
) determine which bytes will be written; all or none may be activated. A write cycle
with no active Byte Write Enable is a no-op cycle.
Partial Truth Table (x36)
Function
Read
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
W
H
L
L
L
L
L
L
BA
X
L
H
H
H
L
H
BB
X
H
L
H
H
L
H
BC
X
H
H
L
H
L
H
BD
X
H
H
H
L
L
H
Operation
This device is pipelined, with double late write functionality, matching the write command versus data pipeline length (2
cycles) to the read command versus data pipeline length (2 cycles). At the first rising clock edge, Enable, Write, Byte
Write(s), and Address are registered. The Data In associated with that address is required at the third rising clock edge.
Burst Cycles
These devices sustain 100% bus bandwidth by eliminating turnaround cycles, and also by performing multiple back-to-
back reads or writes. The on-chip burst address generator further simplifies burst read or write implementations. Driving
ADV high commands the device to advance the internal address counter and use the generated address to read or write.
The starting address for the first cycle in a burst is loaded into the device by driving ADV low.
Burst Order
The burst sequence is determined by the Linear Burst Order pin (
LBO
): Low = Linear, High = Interleaved.
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
Note:
In both cases,
the
burst
counter wraps to initial
state on the 5th clock.
Interleaved Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Output Strength
The LODRV pin selects either nominal drive strength (LODRV low) for multi-drop bus applications or low drive strength
(LODRV floating or high) for point-to-point applications.
Rev. 1.0 – 23 January 2007
Page 4 of 20
©2005, Tezzaron Semiconductor Corp.
Advance Data
TSC3L72T18 / 36
Sleep Mode
Sleep mode is a low current “power-down” mode in which the device is deselected and current is reduced to I
SB
2. The
mode is controlled by ZZ, an asynchronous, active high input. During normal operation, ZZ must be pulled low, either by
the user or by its internal pull down resistor. When ZZ is pulled high, the device enters a Sleep mode after 2 cycles; the
internal state of the device is preserved. When ZZ returns to low, the device resumes normal operation after 2 cycles of
wake up time.
In Sleep mode, all inputs except ZZ are disabled and all outputs go to High-Z. When the ZZ pin is driven high, I
SB
2 is
guaranteed after time tZZI. Because ZZ is an asynchronous input, current or pending operations may not be properly
completed if ZZ is asserted; Sleep mode must not be initiated until valid pending operations are completed. Similarly,
when exiting Sleep mode, only Deselect or Read commands may be applied during tZZR.
W.&
&.
W.+
W./
W==6
W==+
W==5
==
Mode Pin Functions
Mode
Burst Order Control
Pin
Pulled?
no
State
L
H
Down
L or NC
H
L
H or NC
Function
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
High Drive
Low Drive
LBO
ZZ
Power Down Control
Drive Strength Control
LODRV
Up
Note:
There is a pull-up on the LODRV pin and a pull-down on the ZZ pin; if these pins are unconnected, the device operates in the default states (specified by
“NC” in the table).
Rev. 1.0 – 23 January 2007
Page 5 of 20
©2005, Tezzaron Semiconductor Corp.
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