Product Specification
PE83336
Product Description
Peregrine’s PE83336 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The superior
phase noise performance of the PE83336 makes it ideal for
rugged military environments including: radio handsets,
radar, avionics, missiles, etc.
The PE83336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE3336 Phase Locked-Loop is optimized for stringent
military environments. It is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
3000 MHz UltraCMOS
®
Integer-N PLL
For Low Phase Noise Applications
Military Operating Temperature Range
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Ultra-low phase noise
Available in 44-lead CQFJ
Figure 1. Block Diagram
F
in
F
in
Prescaler
10 / 11
Main
Counter
13
f
p
D(7:0)
8
Sdata
Pre_en
M(6:0)
A(3:0)
R(3:0)
f
r
Primary
20-bit
20
Latch
Secon-
dary
20-bit
Latch
20
20
20
16
Phase
Detector
PD_U
PD_D
6
6
f
c
R Counter
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE83336
Product Specification
Figure 2. Pin Configuration (Top View)
GND
DD
Figure 3. Package Photo
GND
6
D
,M
5
4
3
2
1
44
43
42
41
GND
3
2
1
0
Enh
LD
R
R
R
R
V
fr
40
39
f
0
0
7
c
D
1
,M
1
8
38
V
DD
_f
c
D
2
,M
2
9
37
PD_U
D
3
,M
3
10
36
PD_D
V
DD
11
35
V
DD
V
DD
12
34
C
ext
S_WR, D
4
,M
4
13
33
V
DD
Sdata, D
5
,M
5
14
32
D
out
Sclk, D
6
,M
6
15
31
V
DD
_f
p
FSELS, D
7
, Pre_en
16
30
f
p
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
GND
Table 1. Pin Descriptions
Pin No.
(44-lead
CQFJ)
1
2
3
4
5
6
7
Pin
Name
V
DD
R
0
R
1
R
2
R
3
GND
D
0
M
0
D
1
M
1
D
2
M
2
D
3
M
3
V
DD
V
DD
S_WR
FSELP, A
0
E_WR, A
1
Interface
Mode
ALL
Direct
Direct
Direct
Direct
ALL
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
ALL
Serial
Parallel
Direct
M2_WR, A
2
44-lead CQFJ
Smode, A
3
Bmode
V
DD
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
M1_WR
Type
A_WR
Hop_WR
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Document No. 70-0137-05
│
UltraCMOS
®
RFIC Solutions
F
in
F
in
Description
8
9
10
11
12
13
D
4
M
4
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE83336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
CQFJ)
Pin
Name
Sdata
14
D
5
M
5
Sclk
15
D
6
M
6
FSELS
16
D
7
Pre_en
17
GND
FSELP
18
A
0
Direct
Serial
E_WR
19
A
1
M2_WR
20
A
2
Smode
21
A
3
22
23
24
25
26
27
28
29
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
GND
Direct
Serial,
Parallel
Direct
ALL
ALL
Parallel
Parallel
Serial,
Parallel
ALL
ALL
ALL
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Parallel
Direct
Parallel
Input
Input
Input
Input
Input
Interface
Mode
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the
8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Ground.
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the rising
edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of
M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0,
Smode=1) or Parallel Interface Mode (Bmode=0,
Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on the rising edge of
M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
Hop write. The contents of the primary register are latched into the secondary register on the
rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50
Ω
resistor directly to the ground plane.
Ground.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE83336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
CQFJ)
30
31
32
33
Pin
Name
f
p
V
DD
-f
p
Dout
V
DD
Cext
Interface
Mode
ALL
ALL
Serial,
Parallel
ALL
Type
Output
(Note 1)
Output
(Note 1)
Description
Monitor pin for main divider output. Switching activity can be disabled through enhancement
register programming or by floating or grounding V
DD
pin 31.
V
DD
for f
p
. Can be left floating or connected to GND to disable the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Same as pin 1.
PD_D is pulse down when f
p
leads f
c
.
PD_U is pulse down when f
c
leads f
p
.
34
ALL
Output
35
36
37
38
39
40
41
42
43
44
N/A
Note 1:
V
DD
PD_D
PD_U
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
NC
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial,
Parallel
ALL
(Note 1)
Output
(Note 1)
Output
V
DD
for f
c
can be left floating or connected to GND to disable the f
c
output.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V
DD
pin 38.
Ground.
Ground.
Input
Output
Input
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
No connection.
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
V
DD
-f
p
and V
DD
-f
p
are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and
f
c
outputs.
Note 2:
All digital input pins have 70 kΩ pull-down resistors to ground.
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. 70-0137-05
│
UltraCMOS
®
RFIC Solutions
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE83336
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Table 4. ESD Ratings
Units
V
V
mA
mA
°C
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+ 0.3
+10
+10
150
Symbol
V
ESD
Note 1:
Parameter/Conditions
ESD voltage (Human Body
Model)
Level
1000
Units
V
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-55
Max
3.15
125
Units
V
°C
Table 5. DC Characteristics:
V
DD
= 3.0 V, -55° C
≤
T
A
≤
125° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
10
20
Max
Units
mA
mA
28
Digital Inputs: All except f
r
, R
0
, F
in
,
F
in
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-1
0.7 x V
DD
0.3 x V
DD
+70
V
V
µA
µA
Reference Divider input: f
r
I
IHR
I
ILR
High level input current
Low level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
+100
µA
µA
R0 Input (Pull-up Resistor): R
0
I
IHRO
I
ILRO
High level input current
Low level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-5
+70
µA
µA
Counter and phase detector outputs: f
c
, f
p
, PD_D, PD_U
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 6mA
I
out
= -3mA
V
DD
- 0.4
0.4
V
V
Lock detect outputs: Cext, LD
V
OLC
V
OHC
V
OLLD
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
I
out
= 100µA
I
out
= -100µA
I
out
= 6mA
V
DD
- 0.4
0.4
0.4
V
V
V
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