VSC7139,VSC7139 pdf中文资料,VSC7139引脚图,VSC7139电路-Datasheet-电子工程世界

Datasheet> 器件分类 > VSC7139

文档预览

VSC7139: 产品描述Quad Transceiver for Gigabit Ethernet and Fibre Channel; 文件大小247KB，共18页; 制造商Vitesse Semiconductor Corporation; 官网地址http://www.vitesse.com/

下载文档选型对比全文预览

VSC7139概述

Quad Transceiver for Gigabit Ethernet and Fibre Channel

文档预览

下载PDF文档

全文
预览

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Features

• Four Complete Transmitter/ Receiver Functions

in a Single Integrated Circuit

• Full Fibre Channel (T11) and Gigabit Ethernet

(IEEE 802.3z) Compliance

• 1.05Gb/s to 1.36Gb/s Operation per Channel

• Common or Per-Channel Transmit Byte Clocks

• TTL or PECL Reference Clock Input

• 1/10

or 1/20

Baud Rate Recovered Clocks

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

• Common and Per-Channel, Serial and Paral-

lel Loopback Controls

• Common Comma Detect Enable Inputs

• Per-Channel Comma Detect Outputs

• Cable Equalization in Receivers

• Automatic Lock-to-Reference

• 3.3V Power Supply, 2.67 W Max Power

Dissipation

• 208-Pin, 23mm BGA Packaging

General Description

The VSC7139 is a full-speed Quad Fibre Channel and Gigabit Ethernet Transceiver IC. Each of the four

transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters

and serializes the data onto high speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be

synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each

receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters,

outputs a recovered clock and detects “Comma” characters. The VSC7139 contains on-chip (PLL) circuitry for

synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.

VSC7139 Block Diagram (1 of 4 Channels)

Rx(0:9)

Serial to

Q Parallel D

÷10

Clock

Recovery

Rx+

Rx-

RCM

RCx1

RCx0

SYNCx

ENCDET

PLUP

SLPN

LPNx

Tx(0:9)

SEL

÷10/

÷20

Comma

Detect

Loopback

Control

Parallel

to Serial

Tx+

Tx-

TBCx

REFT

REF+

REF-

RFCM

LTCN

Clock

Multiply

Unit

x10/x20

RFCO0

RFCO1

G52196-0, Rev 3.3

5/14/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Preliminary Datasheet

VSC7139

Functional Description

Notation

In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a sig-

nal on any specific channel, the signal will have the Channel letter embedded in the name, i.e., “TA(0:9).” When

referring to the common behavior of a signal which is used on each of the four channels, a lower case “x” is

used in the signal name, i.e. Tx(0:9). Differential signals, i.e. RA+ and RA-, may be referred to as a single sig-

nal, i.e. RA, by dropping reference to the “+” and “-”. “REF” refers to either the TTL input REFT, or the PECL

differential inputs REF+/REF-, whichever is used.

Clock Synthesizer

The VSC7139 clock synthesizer multiplies the reference frequency provided on the REF input by 10 or 20

to achieve a baud rate clock between 1.05GHz and 1.36GHz. The REF input can be either TTL or PECL. If

TTL, connect the TTL input clock to REFT. If PECL, connect the PECL inputs to REF+ and REF-. The internal

clock presented to the Clock Synthesizer is a logical XNOR of REFT and REF+/-. The reference clock will be

active HIGH if the unused input is HIGH. The reference clock is active LOW if the unused input is LOW. REFT

has an internal pull-up resistor. Internal biasing resistors set the proper DC level on REF+/- so AC-coupling may

be used.

The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency locked to the REF input. This

clock is derived from the clock synthesizer and is always 1/10 the baud rate, regardless of the state of the RFCM

input.

The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the

Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working

voltage rating and a good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These

capacitors are used to minimize the impact of common mode noise on the Clock Multiplier Unit (CMU),

especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred

because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor

between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground,

C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor circuit,

a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

CAP0

VSC7139

CAP1

C1=C2=C3= >0.1µF

MultiLayer Ceramic

Surface Mount

NPO (Preferred) or X7R

5V Working Voltage Rating

Page 2

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52196-0, Rev 3.3

5/14/01

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Serializer

The VSC7139 accepts TTL input data as a parallel 10 bit character on the Tx(0:9) bus which is latched into

the input register on the rising edge of either REF or TBCx. Three clocking modes are available and automati-

cally detected by the VSC7139. If TBCC is static and RFCM is HIGH, then all four Tx(0:9) busses are latched

on the rising edges of REF. If TBCC is static and RFCM is LOW, then REF is multiplied by 20 and the input

busses are latched on the rising edges of REF and at the midpoint between rising edges. If TBCC is toggling but

TBCB is static, then all four Tx(0:9) busses are latched on the rising edges of TBCC. If TBCB and TBCC are

both toggling then the rising edge of each TBCx latches the corresponding Tx(0:9) bus.

The active TBCC or TBCx inputs must be frequency-locked to REF. There is no specified phase relation-

ship. Prior to normal data transmission, LTCN must be asserted LOW so that the VSC7139 can lock to TBCx

which may result in corrupted data being transmitted. Once LTCN has been raised HIGH, the transmitters

remain locked to REF and can tolerate +2 bit times of drift in TBCx relative to REF.

The 10-bit parallel transmission character will be serialized and transmitted on the Tx PECL differential

outputs at the baud rate with bit Tx0 (bit a) transmitted first. User data should be encoded using 8B/10B or an

equivalent code. The mapping to 10B encoded bit nomenclature and transmission order is shown in Table 1,

along with the recognized comma pattern.

Table 1: Transmission Order and Mapping of a 10B Character

Data Bit

10B Bit Position

Comma Character

Tx9

Tx8

Tx7

Tx6

Tx5

Tx4

Tx3

Tx2

Tx1

Tx0

Clock Recovery

The VSC7139 accepts differential high speed serial input from the selected source (either the PECL Rx+/

Rx- pins or the internal Tx+/- data), extracts the clock and retimes the data. Equalizers are included in the

receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the

incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by

an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no

external components. For proper operation, the baud rate of the data stream to be recovered should be within

+200 ppm of ten times the REF frequency. For example, Gigabit Ethernet systems would use 125MHz oscilla-

tors with a +100ppm accuracy resulting in +200 ppm between VSC7139 pairs.

Deserializer

The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7139 provides

complementary TTL recovered clocks, RCx0 and RCx1, which are at one-twentieth of the serial baud rate (if

RCM=LOW) or one-tenth (if RCM=HIGH). The clocks are generated by dividing down the high-speed recov-

ered clock which is phase locked to the serial data. The serial data is retimed, deserialized and output on

Rx(0:9).

If serial input data is not present, or does not meet the required baud rate, the VSC7139 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCx0/RCx1 output fre-

quency under these circumstances will differ from its expected frequency by no more than +1%.

G52196-0, Rev 3.3

5/14/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 3

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Word Alignment

Preliminary Datasheet

VSC7139

The VSC7139 provides 7-bit comma character recognition and data word alignment. Word synchronization

is enabled on all channels by asserting ENCDET HIGH. When synchronization is enabled, the receiver exam-

ines the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where

the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/

10B coded data character or pair of adjacent characters. It occurs only within special characters, known as

K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is

defined as any of the following conditions:

1. The comma is not aligned within the 10-bit transmission character such that Rx(0...6) = “0011111”.

2. The comma straddles the boundary between two 10-bit transmission characters.

3. The comma is properly aligned but occurs in the received character presented during the rising edge of

RCx0 rather than RCx1.

When ENCDET is HIGH and an improperly-aligned comma is encountered, the recovered clock is

stretched, never slivered, so that the comma character and recovered clocks are aligned properly to Rx(0:9).

This results in proper character and word alignment. When the parallel data alignment changes in response to a

improperly-aligned comma pattern, data which would have been presented on the parallel output port prior to

the comma character, and possibly the comma character itself, may be lost. Possible loss of the comma charac-

ter is data dependent, according to the relative change in alignment. Data subsequent to the comma character

will always be output correctly and properly aligned. When ENCDET is LOW, the current alignment of the

serial data is maintained indefinitely, regardless of data pattern.

On encountering a comma character, SYNCx is driven HIGH. The SYNCx pulse is presented simulta-

neously with the comma character and has a duration equal to the data. The SYNCx signal is timed such that it

can be captured by the adjoining protocol logic on the rising edge of RCx1. Functional waveforms for synchro-

nization are given in Figure 2. The first K28.5 shows the case where the comma is detected, but it is misaligned

so a change in the output data alignment is required. Note that up to three characters prior to the comma charac-

ter may be corrupted by the realignment process. The second K28.5 shows the case when a comma is detected

and no phase adjustment is necessary. Figure 2 illustrates the position of the SYNCx pulse in relation to the

comma character on Rx(0:9).

Figure 2: Misaligned and Aligned K28.5 Characters

RCx0

(RCM LOW)

RCx1

RCx0

(RCM HIGH)

RCx1

SYNCx

Rx(0:9)

Data

Corrupt

K28.5

Data1

Data2

Data3

K28.5

Misaligned Comma: Stretched

Aligned Comma

Page 4

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52196-0, Rev 3.3

5/14/01

VSC7139相似产品对比

	VSC7139	VSC7139TW
描述	Quad Transceiver for Gigabit Ethernet and Fibre Channel	Quad Transceiver for Gigabit Ethernet and Fibre Channel

VSC7139

VSC7139概述

文档预览

VSC7139相似产品对比

推荐资源