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CD4011BCMX

产品描述Logic Gates Qd 2-Input NAND Gate
产品类别逻辑    逻辑   
文件大小117KB,共9页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
标准
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CD4011BCMX概述

Logic Gates Qd 2-Input NAND Gate

CD4011BCMX规格参数

参数名称属性值
是否Rohs认证符合
零件包装代码SOIC
包装说明SOP, SOP14,.25
针数14
Reach Compliance Codeunknown
系列4000/14000/40000
JESD-30 代码R-PDSO-G14
JESD-609代码e3
长度8.65 mm
负载电容(CL)50 pF
逻辑集成电路类型NAND GATE
湿度敏感等级1
功能数量4
输入次数2
端子数量14
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP14,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源5/15 V
Prop。Delay @ Nom-Sup250 ns
传播延迟(tpd)250 ns
认证状态Not Qualified
施密特触发器NO
座面最大高度1.75 mm
最大供电电压 (Vsup)15 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度3.9 mm
Base Number Matches1

文档预览

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CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
October 1987
Revised March 2002
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
s
Low power TTL:
Fan out of 2 driving 74L compatibility:
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full
temperature range
or 1 driving 74LS
Ordering Code:
Order Number
CD4001BCM
CD4001BCSJ
CD4001BCN
CD4011BCM
CD4011BCN
Package Number
M14A
M14D
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005939
www.fairchildsemi.com

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