PN7120
NFC controller with integrated firmware, supporting all NFC
Forum modes
Rev. 3.4 — 18 October 2017
312434
Product data sheet
COMPANY PUBLIC
1
Introduction
This document describes the functionality and electrical specification of the NFC
Controller PN7120.
Additional documents describing the product functionality further are available for design-
in support. Refer to the references listed in this document to get access to the full for full
documentation provided by NXP.
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
PN7120
2
General description
PN7120, the best plug'n play full NFC solution - easy integration into any OS
environment, with integrated firmware and NCI interface designed for contactless
communication at 13.56 MHz.
It is the ideal solution for rapidly integrating NFC technology in any application, especially
those running OS environment like Linux and Android, reducing Bill of Material (BOM)
size and cost, thanks to:
•
full NFC forum compliancy (see
[11])
with small form factor antenna
•
embedded NFC firmware providing all NFC protocols as pre-integrated feature
2
•
direct connection to the main host or microcontroller, by I C-bus physical and NCI
protocol
•
ultra-low power consumption in polling loop mode
•
Highly efficient integrated power management unit (PMU) allowing direct supply from a
battery
PN7120 embeds a new generation RF contactless front-end supporting various
transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC
15693, ISO/IEC 18000-3, MIFARE and FeliCa specifications. It embeds an ARM Cortex-
M0 microcontroller core loaded with the integrated firmware supporting the NCI 1.0 host
communication.
The contactless front-end design brings a major performance step-up with on one hand
a higher sensitivity and on the other hand the capability to work in active load modulation
communication enabling the support of small antenna form factor
Supported transmission modes are listed in
Figure 1.
For contactless card functionality,
the PN7120 can act autonomously if previously configured by the host in such a manner.
PN7120 integrated firmware provides an easy integration and validation cycle as all the
NFC real-time constraints, protocols and device discovery (polling loop) are being taken
care internally. In few NCI commands, host SW can configure the PN7120 to notify for
card or peer detection and start communicating with them.
NFC FORUM
NFC-IP MODES
READER
(PCD - VCD)
CARD
(PICC)
READER FOR NFC FORUM
TAG TYPES 1 TO 4
P2P ACTIVE
106 TO 424 kbps
INITIATOR AND TARGET
P2P PASSIVE
106 TO 424 kbps
INITIATOR AND TARGET
ISO/IEC 14443 A
ISO/IEC 14443 B
ISO/IEC 15693
MIFARE CLASSIC 1K / 4K
MIFARE DESFire
Sony FeliCa
(1)
ISO/IEC 14443 A
ISO/IEC 14443 B
aaa-015868
1. According to ISO/IEC 18092 (Ecma 340) standard.
Figure 1. PN7120 transmission modes
PN7120
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.4 — 18 October 2017
312434
2 / 58
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
PN7120
3
Features and benefits
•
Includes NXP ISO/IEC 14443-A and Innovatron ISO/IEC 14443-B intellectual property
licensing rights
•
ARM Cortex-M0 microcontroller core
•
Highly integrated demodulator and decoder
•
Buffered output drivers to connect an antenna with minimum number of external
components
•
Integrated RF level detector
•
Integrated Polling Loop for automatic device discovery
•
RF protocols supported
–
NFCIP-1, NFCIP-2 protocol (see
[7]
and
[10])
–
ISO/IEC 14443A, ISO/IEC 14443B PICC mode via host interface (see[2] )
–
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see
[11])
–
FeliCa PCD mode
–
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
–
NFC Forum tag 1 to 4 (MIFARE Ultralight, Jewel, Open FeliCa tag, MIFARE
DESFire) (see
[11])
–
ISO/IEC 15693/ICODE VCD mode (see
[8])
•
Supported host interfaces
–
NCI protocol interface according to NFC Forum standardization (see
[1])
2
–
I C-bus High-speed mode (see[3] )
•
Integrated power management unit
–
Direct connection to a battery (2.3 V to 5.5 V voltage supply range)
–
Support different Hard Power-Down/Standby states activated by firmware
–
Autonomous mode when host is shut down
2
•
Automatic wake-up via RF field, internal timer and I C-bus interface
•
Integrated non-volatile memory to store data and executable code for customization
PN7120
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.4 — 18 October 2017
312434
3 / 58
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
PN7120
4
Applications
•
All devices requiring NFC functionality especially those running in an Android or Linux
environment
•
TVs, set-top boxes, Blu-ray decoders, audio devices
•
Home automation, gateways, wireless routers
•
Home appliances
•
Wearables, remote controls, healthcare, fitness
•
Printers, IP phones, gaming consoles, accessories
PN7120
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.4 — 18 October 2017
312434
4 / 58
NXP Semiconductors
NFC controller with integrated firmware, supporting all NFC Forum modes
PN7120
5
Quick reference data
Table 1. Quick reference data
Symbol
V
BAT
Parameter
battery supply voltage
Conditions
Card Emulation and Passive
Target; V
SS
= 0 V
Reader, Active Initiator and
Active Target; V
SS
= 0 V
V
DD
V
DD(PAD)
supply voltage
internal supply voltage
V
DD(PAD)
supply voltage supply voltage for host
interface
1.8 V host supply;
V
SS
= 0 V
3.3 V host supply;
V
SS
= 0 V
I
BAT
battery supply current
in Hard Power Down state;
V
BAT
= 3.6 V; T = 25 °C
in Standby state;
V
BAT
= 3.6 V; T = 25 °C
in Monitor state;
V
BAT
= 2.75 V; T = 25 °C
in low-power polling loop;
V
BAT
= 3.6 V; T = 25 °C;
loop time = 500 ms
PCD mode at typical 3 V
I
O(VDDPAD)
output current on pin
V
DD(PAD)
current limit threshold
current
total power dissipation
ambient temperature
total current which can
be pulled on V
DD(PAD)
referenced outputs
current limiter on V
DD(TX)
pin; V
DD(TX)
= 3.1 V
Reader; I
VDD(TX)
= 100 mA;
V
BAT
= 5.5 V
JEDEC PCB-0.5
[3][4]
[3]
[1]
[1]
[2]
[1]
[2]
Min
2.3
2.7
Typ
-
-
Max Unit
5.5
5.5
V
V
1.65 1.8
1.95 V
1.65 1.8
3.0
-
-
-
-
-
10
-
-
150
1.95 V
3.6
12
20
12
-
V
μA
μA
μA
μA
[1]
-
-
-
-
170
15
mA
mA
I
th(Ilim)
P
tot
T
amb
[1]
[2]
[3]
[4]
-
-
-30
180
-
+25
-
0.5
+85
mA
W
°C
V
SS
represents V
SS
, V
SS1
, V
SS2
, V
SS3
, V
SS4
, V
SS(PAD)
and V
SS(TX)
.
The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must
be taken into account).
The antenna shall be tuned not to exceed the maximum of I
VBAT
.
This is the threshold of a built-in protection done to limit the current out of V
DD(TX)
in case of any issue at antenna pins
to avoid burning the device. It is not allowed in operational mode to have I
VDD(TX)
such that I
VBAT
maximum value is
exceeded.
PN7120
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.4 — 18 October 2017
312434
5 / 58
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