NCP4305
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4305 is high performance driver tailored to control a
synchronous rectification MOSFET in switch mode power supplies.
Thanks to its high performance drivers and versatility, it can be used in
various topologies such as DCM or CCM flyback, quasi resonant
flyback, forward and half bridge resonant LLC.
The combination of externally adjustable minimum off-time and
on-time blanking periods helps to fight the ringing induced by the PCB
layout and other parasitic elements. A reliable and noise less operation
of the SR system is insured due to the Self Synchronization feature. The
NCP4305 also utilizes Kelvin connection of the driver to the MOSFET
to achieve high efficiency operation at full load and utilizes a light load
detection architecture to achieve high efficiency at light load.
The precise turn−off threshold, extremely low turn−off delay time
and high sink current capability of the driver allow the maximum
synchronous rectification MOSFET conduction time and enables
maximum SMPS efficiency. The high accuracy driver and 5 V gate
clamp enables the use of GaN FETs.
Features
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MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
8
NCP4305x
ALYW
G
G
1
1
DFN8
MN SUFFIX
CASE 488AF
4305x
ALYWG
G
1
WDFN8
MT SUFFIX
CASE 511AT
5xMG
G
•
Self−Contained Control of Synchronous Rectifier in CCM, DCM and
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
QR for Flyback, Forward or LLC Applications
Precise True Secondary Zero Current Detection
4305x = Specific Device Code
Typically 12 ns Turn off Delay from Current Sense Input to Driver
x = A, B, C, D or Q
Rugged Current Sense Pin (up to 200 V)
A
= Assembly Location
Ultrafast Turn−off Trigger Interface/Disable Input (7.5 ns)
L
= Wafer Lot
Y
= Year
Adjustable Minimum ON−Time
W
= Work Week
Adjustable Minimum OFF-Time with Ringing Detection
M
= Date Code
G
= Pb−Free Package
Adjustable Maximum ON−Time for CCM Controlling of Primary
QR Controller
(Note: Microdot may be in either location)
Improved Robust Self Synchronization Capability
ORDERING INFORMATION
8 A / 4 A Peak Current Sink / Source Drive Capability
See detailed ordering and shipping information on page 49 of
Operating Voltage Range up to V
CC
= 35 V
this data sheet.
Automatic Light−load & Disable Mode
Typical Applications
Adaptive Gate Drive Clamp
•
Notebook Adapters
GaN Transistor Driving Capability (options A and C)
•
High Power Density AC/DC Power Supplies (Cell
Low Startup and Disable Current Consumption
Phone Chargers)
Maximum Operation Frequency up to 1 MHz
•
LCD TVs
SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages
•
All SMPS with High Efficiency Requirements
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 3
Publication Order Number:
NCP4305/D
NCP4305
Figure 1. Typical Application Example − LLC Converter with Optional LLD and Trigger Utilization
Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter with optional LLD and Disabled
TRIG
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NCP4305
Figure 3. Typical Application Example − Primary Side Flyback Converter with optional LLD and Disabled TRIG
Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy
Loads utilizing MAX−TON
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3
NCP4305
PIN FUNCTION DESCRIPTION
ver. A, B, C, D
1
2
3
4
5
ver. Q
1
2
3
4
−
Pin Name
VCC
MIN_TOFF
MIN_TON
LLD
TRIG/DIS
Supply voltage pin
Adjust the minimum off time period by connecting resistor to ground.
Adjust the minimum on time period by connecting resistor to ground.
This input modulates the driver clamp level and/or turns the driver off during light load
conditions.
Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applica-
tions in order to improve efficiency. Activates disable mode if pulled−up for more than
100
ms.
Current sense pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can
decrease the turn off threshold if needed.
Ground connection for the SR MOSFET driver and V
CC
decoupling capacitor. Ground
connection for minimum on and off time adjust resistors, LLD and trigger inputs.
GND pin should be wired directly to the SR MOSFET source terminal/soldering point
using Kelvin connection. DFN8 exposed flag should be connected to GND
Driver output for the SR MOSFET
Adjust the maximum on time period by connecting resistor to ground.
Description
6
6
CS
7
7
GND
8
−
8
5
DRV
MAX_TON
MIN_TON
ADJ
ELAPSED
Minimum ON time
generator
EN
V
DD
100mA
DISABLE
Disable detection
&
V DRV clamp
modulation
V_DRV
control
LLD
CS
CS_ON
DRIVER
DRV Out
DRV
CS
detection
CS_OFF
CS_RESET
Control logic
V
DD
RESET
MIN_TOFF
ADJ
Minimum OFF
time generator
ELAPSED
EN
DISABLE
V
CC
managment
UVLO
VCC
TRIG
DISABLE
TRIG/ DISABLE
10 A
V
trig
Disable detection
GND
Figure 5. Internal Circuit Architecture − NCP4305A, B, C, D
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NCP4305
ELAPSED
MIN_TON
ADJ
Minimum ON time
generator
EN
DISABLE
Disable detection
&
V DRV clamp
modulation
V_DRV
control
LLD
V
DD
100mA
CS
CS_ON
DRIVER
DRV Out
DRV
CS
detection
CS_OFF
CS_RESET
Control logic
V
DD
RESET
MIN_TOFF
ADJ
Minimum OFF
time generator
ELAPSED
EN
DISABLE
V
CC
managment
UVLO
VCC
ELAPSED
MAX_TON
ADJ
Maximum ON time
generator
GND
EN
Figure 6. Internal Circuit Architecture − NCP4305Q (CCM QR) with MAX_TON
ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
TRIG/DIS, MIN_TON, MIN_TOFF, MAX_TON, LLD Input Voltage
Symbol
V
CC
V
TRIG/DIS
,
V
MIN_TON
,
V
MIN_TOFF
,
V
MAX_TON
, V
LLD
V
DRV
V
CS
V
CS_DYN
I
MIN_TON
, I
MIN_TOFF
,
I
MAX_TON
, I
LLD
, I
TRIG
R
qJ−A_SOIC8
R
qJ−A_DFN8
R
qJ−A_WDFN8
T
JMAX
T
STG
ESD
HBM
ESD
HBM
ESD
MM
ESD
CDM
ESD
CDM
Value
−0.3 to 37.0
−0.3 to V
CC
Unit
V
V
Driver Output Voltage
Current Sense Input Voltage
Current Sense Dynamic Input Voltage (t
PW
= 200 ns)
MIN_TON, MIN_TOFF, MAX_TON, LLD, TRIG Input Current
Junction to Air Thermal Resistance, 1 oz 1 in
2
Copper Area, SOIC8
Junction to Air Thermal Resistance, 1 oz 1 in
2
Copper Area, DFN8
Junction to Air Thermal Resistance, 1 oz 1 in
2
Copper Area, WDFN8
Maximum Junction Temperature
Storage Temperature
ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E
ESD Capability, Human Body Model, Pin 6, per JESD22−A114E
ESD Capability, Machine Model, per JESD22−A115−A
ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F
ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F
−0.3 to 17.0
−4 to 200
−10 to 200
−10 to 10
160
80
160
150
−60 to 150
2000
1000
200
750
250
V
V
V
mA
°C/W
°C/W
°C/W
°C
°C
V
V
V
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.
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