74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Rev. 03 — 20 March 2006
Product data sheet
1. General description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where
two separate data paths must be multiplexed onto, or demultiplexed from, a single data
path. Typical applications include multiplexing or demultiplexing of address and data
information in microprocessor or bus-interface applications. This device is also useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1 to A12, 1B1 to 1B12 and 2B1 to 2B12) are available for address
or data transfer. The output enable inputs (OE1B, OE2B, and OEA) control the bus
transceiver functions. OE1B and OE2B also allow bank control in the A to B direction.
Address or data information can be stored using the internal storage latches. The latch
enable inputs (LE1B, LE2B, LEA1B and LEA2B) are used to control data storage. When
the latch enable input is HIGH, the latch is transparent. When the latch enable input goes
LOW, the data present at the inputs is latched and remains latched until the latch enable
input is returned HIGH.
To ensure the high-impedance state during power-up or power-down, all output enable
inputs should be tied to V
CC
through a pull-up resistor. The minimum value of the resistor
is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a SSOP56 and a TSSOP56 package.
2. Features
I
I
I
I
I
I
I
I
5 V I/O compatible
Bus hold inputs eliminate the need for external pull-up resistors
Live insertion and extraction permitted
Power-up 3-state
Power-up reset
Output capability: +64 mA and
−32
mA
Distributed V
CC
and GND pin configuration minimizes high-speed switching noise
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 883C, method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
Philips Semiconductors
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
V
CC
= 2.5 V
I
CC
quiescent supply current
V
CC
= 2.7 V;
V
I
= GND or V
CC
;
I
O
= 0 A;
outputs disabled
C
L
= 50 pF
C
L
= 50 pF
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
V
CC
= 3.6 V;
V
I
= GND or V
CC
;
I
O
= 0 A;
outputs disabled
C
L
= 50 pF
C
L
= 50 pF
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
[1]
[1]
Conditions
Min
-
Typ
40
Max Unit
-
µA
t
PLH
t
PHL
C
i
C
io
I
CC
LOW-to-HIGH propagation delay
An to xBn; xBn to An
HIGH-to-LOW propagation delay
An to xBn; xBn to An
input capacitance (control pins)
input/output capacitance (I/O pins)
quiescent supply current
-
-
2.8
2.7
4
9
-
-
-
-
-
ns
ns
pF
pF
µA
V
CC
= 3.3 V
-
60
t
PLH
t
PHL
C
i
C
io
[1]
LOW-to-HIGH propagation delay
An to xBn; xBn to An
HIGH-to-LOW propagation delay
An to xBn; xBn to An
input capacitance (control pins)
input/output capacitance (I/O pins)
-
-
2.2
2.0
4
9
-
-
-
-
ns
ns
pF
pF
I
CC
is measured with outputs pulled up to V
CC
or pulled down to ground.
4. Ordering information
Table 2.
Ordering information
Package
Temperature range
74ALVT16260DL
−40 °C
to +85
°C
Name
SSOP56
Description
plastic shrink small outline package; 56 leads; body
width 7.5 mm
Version
SOT371-1
SOT364-1
Type number
74ALVT16260DGG
−40 °C
to +85
°C
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
74ALVT16260_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 March 2006
2 of 18
Philips Semiconductors
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Pin description
…continued
Pin
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Description
data input/output A2
data input/output A3
ground (0 V)
data input/output A4
data input/output A5
data input/output A6
data input/output A7
data input/output A8
data input/output A9
ground (0 V)
data input/output A10
data input/output A11
data input/output A12
supply voltage
1 data input/output B1
1 data input/output B2
ground (0 V)
1 data input/output B3
latch 2B to A enable input
select B1 or B2 input
output 1B enable input (active LOW)
latch A to 1B enable input
data input/output B4
ground (0 V)
1 data input/output B5
1 data input/output B6
supply voltage
1 data input/output B7
1 data input/output B8
1 data input/output B9
ground (0 V)
1 data input/output B10
1 data input/output B11
1 data input/output B12
2 data input/output B12
2 data input/output B11
2 data input/output B10
ground (0 V)
2 data input/output B9
2 data input/output B8
2 data input/output B7
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table 3.
Symbol
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
OE1B
LEA1B
1B4
GND
1B5
1B6
V
CC
1B7
1B8
1B9
GND
1B10
1B11
1B12
2B12
2B11
2B10
GND
2B9
2B8
2B7
74ALVT16260_3
Product data sheet
Rev. 03 — 20 March 2006
5 of 18
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