Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3.
JC
, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Bias Supply Current
PWM INPUT
Input Current
These specifications apply for T
A
= -40°C to 85°C, unless otherwise noted
SYMBOL
I
VCC
I
VCC
I
PWM
TEST CONDITIONS
EN = LOW, T
A
= 0°C to 70°C
EN = LOW, T
A
= -40°C to 85°C
PWM pin floating, V
VCC
= 5V
V
PWM
= 5V
V
PWM
= 0V
V
VCC
= 5V, T
A
= 0°C to 70°C
V
VCC
= 5V, T
A
= -40°C to 85°C
V
VCC
= 5V
V
VCC
= 5V, temperature = 25°C
MIN
-
-
-
-
-
-
-
3.3
-
1.0
-
t
RUGATE
t
RLGATE
t
FUGATE
t
FLGATE
t
PDLUGATE
t
PDLLGATE
R
UGATE
I
UGATE
R
UGATE
I
UGATE
R
LGATE
I
LGATE
R
LGATE
I
LGATE
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
V
VCC
= 5V, 3nF Load
500mA Source Current
V
UGATE-PHASE
= 2.5V
500mA Sink Current
V
UGATE-PHASE
= 2.5V
500mA Source Current
V
LGATE
= 2.5V
500mA Sink Current
V
LGATE
= 2.5V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
-
-
30
250
-250
-
-
-
420
-
-
8
8
8
4
8
8
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
MAX
1.5
2
-
-
-
1.70
1.75
-
-
-
2.0
-
-
-
-
-
-
2.5
-
2.5
-
2.5
-
1.0
-
UNITS
A
A
A
A
A
V
V
V
ns
V
V
ns
ns
ns
ns
ns
ns
A
A
A
A
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Holdoff Time
EN INPUT
EN LOW Threshold
EN HIGH Threshold
SWITCHING TIME
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
OUTPUT
Upper Drive Source Resistance
Upper Driver Source Current (Note 4)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 4)
Lower Drive Source Resistance
Lower Driver Source Current (Note 4)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 4)
NOTE:
4. Guaranteed by design. Not 100% tested in production.
FN9091 Rev 7.00
May 9, 2006
Page 4 of 10
ISL6605
Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
PINOUT diagrams for QFN pin numbers.
Thermal Pad (in QFN only)
In the QFN package, the pad underneath the center of the
IC is a thermal substrate. The PCB “thermal land” design
for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
Description
Operation
Designed for speed, the ISL6605 MOSFET driver controls both
high-side and low-side N-Channel FETs from one externally
provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[t
PDHUGATE
] based on how quickly the LGATE voltage
drops below 1V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-
through. Once this delay period is completed the upper gate
drive begins to rise [t
RUGATE
] and the upper MOSFET turns
on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLUGATE
] is encountered before the
upper gate begins to fall [t
FUGATE
]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
t
PDHLGATE
. The upper MOSFET gate voltage is monitored
and the lower gate is allowed to rise after the upper MOSFET
gate-to-source voltage drops below 1V. The lower gate then
rises [t
RLGATE
], turning on the lower MOSFET.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see the
three-state PWM Input section under DESCRIPTION for further
details). Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
EN (Pin 7)
Enable input pin. Connect this pin to HIGH to enable and
LOW to disable the IC. When disabled, the IC draws less
than 1A bias current.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. This pin provides a return path
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
