PFS7523-7529/7533-7539
HiperPFS-3
Family
PFC Controller with Integrated High-Voltage MOSFET and Qspeed
Diode Optimized for High PF and Efficiency Across Load Range
Key Benefits
D
K
•
High efficiency and power factor across load range
•
>95% efficiency from 10% load to full load
•
<60 mW no-load consumption at 230 VAC
•
PF >0.92 easily achievable at 20% load
•
EN61000-3-2 Class C and D compliant
•
Highly integrated for smallest boost PFC form factor
•
Integrated controller, MOSFET and ultra-low reverse recovery loss
+
PG
VCC
CONTROL
FB
C
VCC
diode (Qspeed)
•
Packaging optimized for high volume production
•
Eliminates insulating pad/heat-spreader
•
Enhanced features
•
Programmable Power Good (PG) signal
•
User selectable power limit: Enables different HiperPFS-3 family
AC
IN
HiperPFS-3
PGT
DC
OUT
S
V
G
REF
•
•
•
•
members to be tested in the same design for optimum device
selection
•
Integrated non-linear amplifier for fast output OV and UV
protection and transient response
•
Digital line peak detection that provides robust performance even
with distorted input voltage from UPS or generators
•
Digital power factor enhancer compensates for EMI filter and
bridge distortion, providing high-line PF >0.92 @ 20% load
Frequency adjusted over line voltage and each line cycle
•
Spread-spectrum across >60 kHz window simplifies EMI filtering
requirements
•
Lower boost inductance
Provides up to 450 W peak output power for universal
applications, 1 kW for high-line only applications
Protection features include: UVLO, UV, OV, OTP, brown-in/out,
cycle-by-cycle current limit and power limiting for overload
protection
Halogen free and RoHS compliant
PC
Printer
LCD TV
Video game consoles
80 Plus™ Platinum
designs
•
•
•
•
PI-7224-061615
Figure 1.
Typical Application Schematic.
Output Power Table
Universal Input Devices
Product
PFS7523L/H
PFS7524L/H
PFS7525L/H
PFS7526H
PFS7527H
PFS7528H
PFS7529H
Maximum Continuous
Output Power Rating at
90 VAC (Full Power Mode)
110 W
130 W
185 W
230 W
290 W
350 W
405 W
High-Line Only Input Devices
Product
PFS7533H
PFS7534H
PFS7535H
PFS7536H
PFS7537H
PFS7538H
PFS7539H
Table 1.
Peak Output Power
(Full Power Mode)
120 W
150 W
205 W
260 W
320 W
385 W
450 W
Applications
•
•
•
•
•
High-power adaptors
High-power LED lighting
Industrial and appliance
Generic PFC converters
Maximum Continuous
Peak Output Power
Output Power Rating at
(Full Power Mode)
180 VAC (Full Power Mode)
255 W
315 W
435 W
550 W
675 W
810 W
900 W
280 W
350 W
480 W
610 W
750 W
900 W
1000 W
Output Power Table (See Table 2 on page 11 for Maximum Continuous
Output Power Ratings.)
eSIP-16D (H Package)
eSIP-16G (L Package)
Figure 2.
Package Options.
www.power.com
June 2015
This Product is Covered by Patents and/or Pending Patent Applications.
PFS7523-7529/7533-7539
Description
The HiperPFS
™
-3 devices incorporate a continuous conduction mode
(CCM) boost PFC controller, gate driver, ultra-low reverse recovery
(Qspeed
™
) diode and high-voltage power MOSFET in a single,
low-profile (GROUND pin connected) power package. HiperPFS-3
devices eliminate the PFC converter’s need for external current sense
resistors and the associated power loss, and use an innovative control
technique that adjusts the switching frequency over output load,
input line voltage, and even input line cycle.
This control technique maximizes efficiency over the entire load range
of the converter, particularly at light loads. Additionally, it significant-
ly minimizes the EMI filtering requirements due to its wide bandwidth
spread spectrum effect. The HiperPFS-3 uses advanced digital
techniques for line monitoring functions, line feed-forward scaling, and
power factor enhancement, while using analog techniques for the
core controller in order to maintain extremely low no-load power
consumption. The HiperPFS-3 also features an integrated non-linear
error amplifier for enhanced load transient response, a user program-
mable Power Good (PG) signal as well as user selectable power limit
functionality. HiperPFS-3 includes Power Integrations’ standard set of
comprehensive protection features, such as integrated UV, OV,
brown-in/out, and hysteretic thermal shutdown. HiperPFS-3 also
provides cycle-by-cycle current limit and Safe Operating Area (SOA)
protection of the power MOSFET, power limiting of the output for
overload protection, and pin-to-pin short-circuit protection.
HiperPFS-3’s innovative variable frequency continuous conduction
mode operation (VF-CCM) minimizes switching losses by maintaining
a low average switching frequency, while modulating the switching
frequency in order to suppress EMI, the traditional challenge with
continuous conduction mode solutions. Systems using HiperPFS-3
typically reduce the total X and Y capacitance requirements of the
converter, the inductance of both the boost choke and EMI noise
suppression chokes, thereby reducing overall system size and cost.
Additionally, HiperPFS-3 devices dramatically reduce component count
and board footprint while simplifying system design and enhancing
reliability, when compared with designs that use discrete MOSFETs
and controllers. The innovative variable frequency, continuous
conduction mode controller enables the HiperPFS-3 to realize all of
the benefits of continuous conduction mode operation while leverag-
ing low-cost, small, simple EMI filters.
Many regions mandate high power factor for many electronic
products with high power requirements. These rules are combined
with numerous application-specific standards that require high power
supply efficiency across the entire load range, from full load to as low
as 10% load. High efficiency at light load is a challenge for traditional
PFC solutions in which fixed MOSFET switching frequencies cause
fixed switching losses on each cycle, even at light loads. In addition
to featuring relatively flat efficiency across the load range, HiperPFS-3
also enables high power factor of >0.92 at 20% load. HiperPFS-3
simplifies compliance with new and emerging energy-efficiency
standards over a broad market space in applications such as PCs, LCD
TVs, notebooks, appliances, pumps, motors, fans, printers and LED
lighting.
HiperPFS-3’s advanced power packaging technology and high
efficiency simplify the complexity of mounting the IC and thermal
management, while providing very high power capabilities in a single
compact package; these devices are suitable for PFC applications
from 75 W to 900 W.
Product Highlights
Protected Power Factor Correction Solution
•
Incorporates high-voltage power MOSFET, ultra-low reverse
recovery loss Qspeed diode, controller and gate driver.
•
EN61000-3-2 Class C and Class D compliance.
•
Integrated protection features reduce external component count.
•
Accurate built-in brown-in/out protection.
•
Accurate built-in undervoltage (UV) protection.
•
Accurate built-in overvoltage (OV) protection.
•
Hysteretic thermal shutdown (OTP).
•
Internal power limiting function for overload protection.
•
Cycle-by-cycle power switch current limit.
•
Internal non-linear error amplifier for enhanced load transient
response.
•
No external current sense resistor required.
•
Provides ‘lossless’ internal sensing via sense-FET.
•
Reduces component count and system losses.
•
Minimizes high current gate drive loop area.
•
Minimizes output overshoot and stresses during start-up
•
Integrated power limit.
•
Improved dynamic response.
•
Digitally controlled input line feed-forward gain adjustment for
flattened loop gain across entire input voltage range.
•
Eliminates up to 40 discrete components for higher reliability and
lower cost.
Solution for High Efficiency, Low EMI and High PF
•
Continuous conduction mode PFC uses novel constant amp-second
[on-time] volt-second [off-time] control engine.
•
High efficiency across load.
•
High power factor across load.
•
Low cost EMI filter.
•
Frequency sliding technique for light load efficiency improvements.
•
>95% efficiency from 10% load to full load achievable at
nominal input voltages.
•
Variable switching frequency to simplify EMI filter design.
•
Varies over line input voltage to maximize efficiency and
minimize EMI filter requirements.
•
Varies with input line cycle voltage by >60 kHz to maximize
spread spectrum effect.
Advanced Package for High Power Applications
•
Up to 450 W [universal], 1 kW [high-line only] peak output power
capability in a highly compact package.
•
Simple adhesive or clip mounting to heat sink.
•
No insulation pad required and can be directly connected to heat
sink.
•
Staggered pin arrangement for simple routing of board traces and
high-voltage creepage requirements.
•
Single package solution for PFC converter reduces assembly costs
and layout size.
2
Rev. A 06/15
www.power.com
PFS7523-7529/7533-7539
Pin Functional Description
BIAS POWER (VCC) Pin:
This is a 10.2-15 VDC [operating, 12 V typical] bias supply used to
power the IC. The bias voltage must be externally clamped to
prevent the BIAS POWER pin from exceeding 15 VDC to ensure
long-term reliability.
REFERENCE (REF) Pin:
This pin is connected to an external bypass capacitor and is used to
program the IC for either FULL or EFFICIENCY power mode. The
external capacitor is connected between the REFERENCE and SIGNAL
GROUND [G] pins. Note: the return trace to G must not be shared with
other return traces with a potential for large return currents during
surge events. The REFERENCE pin has two valid capacitor values to
select ‘Full’ (1.0
µF
±20%) and ‘Efficiency’ (0.1
µF
±20%) power
modes.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including loop
compensation, decoupling capacitors for the BIAS POWER (VCC),
REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to
the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also
connected to the tab of the device. The SIGNAL GROUND pin should
not be tied directly to the SOURCE pin external to the IC.
VOLTAGE MONITOR (V) Pin:
The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC
rail through a 100:1, 1% high-impedance resistor divider to minimize
power dissipation and standby power consumption. The recommend-
ed resistance value is between 8 MΩ and 16 MΩ. Modifying this
divider ratio affects peak power limit, brown-in/out thresholds and
will degrade input current quality (reduce power factor and increase
THD). A small ceramic capacitor forming an 80
µs
nominal time-
constant is required from the VOLTAGE MONITOR pin to the SIGNAL
GROUND pin to bypass any switching noise present on the rectified
DC bus.
This pin also features brown-in/out detection thresholds and
incorporates a weak current source into the IC in order to act as a
pull-down in the event of an open circuit condition.
COMPENSATION (C) Pin:
This pin is used for loop pole/zero compensation of the OTA error
amplifier via the connection of a network of capacitors and a resistor
between the COMPENSATION pin and SIGNAL GROUND pin. The
COMPENSATION pin connects internally to the output of the OTA error
amplifier and the input to the on-time and off-time controllers.
FEEDBACK (FB) Pin:
This pin is connected to the main voltage regulation feedback resistor
divider network and is also used for fast over and undervoltage
protection. This pin also detects the presence of the feedback
voltage divider network at start-up and during operation. The divider
ratio should be the same as the VOLTAGE MONITOR pin for proper and
optimized power limit and power factor. A large upper resistor
between 8 MΩ and 16 MΩ ±1% is recommended. A small ceramic
capacitor between FEEDBACK and SIGNAL GROUND, forming a nominal
80
µs
time-constant with the bottom resistor, is required.
POWER GOOD (PG) Pin:
Use of the PG function is optional. The POWER GOOD pin is an
active low, open-drain connection which sinks current when the
output voltage is in regulation. At start-up, once the FEEDBACK pin
voltage has risen to ~95% of the internal reference voltage, the
POWER GOOD pin is asserted low.
After start-up, the output voltage threshold at which the PG signal
becomes high-impedance depends on the threshold programmed by
the POWER GOOD THRESHOLD pin resistor. When not in use, the
POWER GOOD pin is left unconnected.
POWER GOOD THRESHOLD (PGT) Pin:
This pin is used to program the output voltage threshold at which the
PG signal becomes high-impedance representing the PFC stage falling
out of regulation. The low threshold for the PG signal is programmed
with a resistor between the POWER GOOD THRESHOLD and SIGNAL
GROUND pins. Tying POWER GOOD THRESHOLD to the REFERENCE
pin disables the power good function (i.e. POWER GOOD pin remains
high impedance).
SOURCE (S) Pins:
These pins are the source connection of the power switch as well as
the negative bulk capacitor terminal connection.
H Package (eSIP-16D)
(Front View)
Pin 1 I.D.
1
VCC
G
3 4 5 6 7 8 91011 1314 16
S
S
PGT
PG
FB
C
V
G
REF
NC
D
K
G
Exposed Metal (Both H and L
Packages) (On Package Edge)
Internally Connected to G Pin
Exposed Pad (Backside)
Internally Connected to
GROUND (G) Pin
H Package
(eSIP-16D)
(Back View)
16 1413 11 9 8 7 6 5 4 3
10
K
1
VCC
1
VCC
REF
G
V
C
FB
PG
PGT
S
S
6
C
L Package (eSIP-16G)
(Front View)
D
NC
4
G
Pin 1 I.D.
8 10
PG
S
13
D
16
K
Exposed Pad
(Backside)
Not Shown
3
REF
5
V
7
9 11
S
14
NC
PI-7225-061615
FB
PGT
Figure 3.
Pin Configuration.
3
www.power.com
Rev. A 06/15
PFS7523-7529/7533-7539
DRAIN (D)
BOOST DIODE CATHODE (K)
BIAS POWER (VCC)
VOLTAGE MONITOR (V)
INPUT LINE INTERFACE
V
V
ADC
PEAK
DETECTOR
PF
ENHANCER
LOW/HIGH
LINE DETECT
12 V GATE DRIVER
REF SERIES/SHUNT
REGULATOR
+
-
UVLO
BROWN-IN/
OUT DETECT
Integrated Qspeed
Ultrafast Diode
Off-Time Controller
M
OFF
×
(V
FB
- V
V
)
C
INT
~(V
O-
V
IN
)
-
+
BO, BI
HL/LL
M
ON(PFE)
I
OCP
REFERENCE
(REF)
V
BRST
FB
REF
V
PG(H)
FB
UV
FB
OFF
FB
OV
VCC
REFERENCE
AND BAND GAP
I
PGT
P
ON
V
OFF
is a function of the error-voltage
(V
E
) and is used to reduce
the average operating frequency
as a function of output power
TIMER
SUPERVISOR
Latch
-
+
+
-
+
-
+
-
FEEDBACK Pin
OV/UV/OFF
Power
MOSFET
senseFET
VCC
V
OFF
V
E
Feedback OV
-
+
FB
OV
V
OFF
Frequency
Slide
V
E
HL/LL
Non-Linear OTA
+
FB
REF
FEEDBACK
(FB)
Feedback UV
Buffer and
De-Glitch
Filter
I
SNS
LEB
OTA
-
I
OCP
+
-
OCP
POWER LIMIT
SOA RAMP
-
+
FB
UV
HL/LL
V
BRST
Feedback OFF
-
+
On-Time Controller
C
INT
FB
OFF
P
ON
×
M
ON(PFE)
×
I
SNS
M
ON(PFE)
is the switch
current sense scale
factor which is a function
of the peak input voltage
START-UP,
FMEA CHECKS
+
-
V
FB
V
PG(H)
REF
I
PGT
POWER GOOD
THRESHOLD
(PGT)
POWER GOOD
(PG)
SOURCE (S)
SIGNAL GROUND (G)
COMPENSATION (C)
PI-7226-062215
Figure 4.
Functional Block Diagram.
DRAIN (D) Pin:
This is the drain connection of the internal power switch.
BOOST DIODE CATHODE (K) Pin:
This is the cathode connection of the internal Qspeed Diode.
Since the volt-seconds during the on-time must equal the volt-sec-
onds during the off-time, to maintain flux equilibrium in the PFC
choke, the on-time (t
ON
) is controlled such that:
(2)
The controller also sets a constant value of charge during each
on-cycle of the power MOSFET. The charge per cycle is varied
gradually over many switching cycles in response to load changes so
it can be regarded as substantially constant for a half line cycle. With
this constant charge (or amp-second) control, the following relation-
ship is therefore also true:
Functional Description
The HiperPFS-3 is a variable switching frequency boost PFC solution.
More specifically, it employs a constant amp-second on-time and
constant volt-second off-time control algorithm. This algorithm is
used to regulate the output voltage and shape the input current to
comply with regulatory harmonic current limits (high power factor).
Integrating the switch current and controlling it to have a constant
amp-sec product over the on-time of the switch allows the average
input current to follow the input voltage. Integrating the difference
between the output and input voltage maintains a constant volt-
second balance dictated by the electro-magnetic properties of the
boost inductor and thus regulates the output voltage and power.
More specifically, the control technique sets constant volt-seconds for
the off-time (t
OFF
). The off-time is controlled such that:
^
V
O
-
V
IN
h
#
t
OFF
=
K
1
(1)
V
IN
#
t
ON
=
K
1
I
IN
#
t
ON
=
K
2
Substituting t
ON
from (2) into (3) gives:
(3)
I
IN
=
V
IN
#
K
2
K
1
(4)
The relationship of (4) demonstrates that by controlling a constant
amp-second on-time and constant volt-second off-time, the input
current I
IN
is proportional to the input voltage V
IN
, therefore providing
the fundamental requirement of power factor correction.
4
Rev. A 06/15
www.power.com
PFS7523-7529/7533-7539
This control produces a continuous mode power switch current
waveform that varies both in frequency and peak current value across
a line half-cycle to produce an input current proportional to the input
voltage.
Control Engine
The controller features a low bandwidth, high gain OTA error-amplifi-
er of which its non-inverting terminal is connected to an internal
voltage reference of 3.85 V. The inverting terminal of the error-am-
plifier is available on the external FEEDBACK pin which connects to
the output voltage divider network with a divider ratio of 1:100 to
regulate the output voltage to 385 V nominally. The FEEDBACK pin
connects directly to the divider network for fast transient load
response.
The internally sensed FET switch current is scaled by the input
voltage peak detector current sense gain (M
ON
) then integrated and
compared with the error-amplifier signal (V
E
) to determine the cycle
on-time. Internally the difference between the input and output
voltage is derived and the resultant is scaled, integrated, and
compared to a voltage reference (V
OFF
) to determine the cycle
off-time. Careful selection of the internal scaling factors produces
input current waveforms with very low distortion and high power
factor.
Line Feed-Forward Scaling Factor (M
ON
) and PF Enhancer
The VOLTAGE MONITOR (V) pin voltage is sampled and converted by
a
Δ-Σ
ADC to a quantized digital value. A digital line cycle peak detec-
tor, with dynamic time constants and multi-cycle filtering, derives and
smooths the peak of the input line voltage. This peak is used
internally to scale the gain of the current sense signal through the
M
ON
variable. This contribution is required to reduce the dynamic
range of the control feedback signal as well as flatten the loop gain
over the operating input line range. The line-sense feed-forward gain
adjustment is proportional to the square of the peak rectified AC line
voltage and is adjusted as a function of the VOLTAGE MONITOR pin
voltage.
At high-line and light load, the feed-forward M
ON
variable is dynami-
cally adjusted throughout the line cycle in order to compensate for
the line current distortion through the EMI filter and full bridge
network, thereby improving power factor.
PI-5335-061615
The line-sense feed-forward gain is also important in providing a
switch power limit over the input line range.
This characteristic is optimized to maintain a relatively constant
internal error-voltage level at full load from an input line of 90 to
230 VAC.
Beyond the specified peak power rating of the device, the internal
power limit feature will regulate the output voltage below the set
regulation threshold as a function of output overload to maintain a
constant output power. Figure 6 illustrates the typical regulation
characteristic as a function of load.
Below the brown-in threshold (V
BR+
) the power limit is reduced when
the device is operated in the ‘Full’ power mode as shown in Figure 7.
As the input line voltage is reduced toward the brown-out threshold
(V
BR-
) and if the load exceeds the power limit derating, the boost
output voltage will drop out of regulation in accordance with Figure 6.
The rated peak power shown in Table 1 is not derated for voltages
below the brown-in threshold when the device is operated in the
‘Efficiency’ mode.
Start-Up with Pin-to-Pin Short-Circuit Protection
At start-up, the engine performs a sequence of operational checks
and pin short/open evaluations, as illustrated in Figure 8, prior to the
commencement of switching. When the input voltage peak is above
brown-in, the engine enables switching.
The OTA error amplifier provides a non-linear amplifier (NLA)
mechanism to overcome the inherently slow feedback loop response
when the sensed output voltage on the FEEDBACK pin is outside its
regulation window. This allows the error amplifier function to limit
the maximum overshoot and undershoot during load transient events.
To reduce switch and output diode current stress at start-up, the
HiperPFS-3 calculates off-time based upon output voltage (V
OUT
) during
start-up, resulting in a relatively soft controlled start-up.
Once the applied VCC is above the VCC
UVLO+
threshold, and the output
of the on-chip V
REF
regulator is above REF
UV+
, the value of the
REFERENCE pin capacitor is detected and the full or efficiency power
mode is latched. The pin open/short tests are performed, and if the
FEEDBACK pin voltage is valid the over-temperature OTP is checked
to be false. Once the preceding checks are satisfied the input voltage
is monitored via the VOLTAGE MONITOR pin until it exceeds the V
BR+
threshold [but the peak detector is not saturated]. It is at this point
that switching is enabled.
Timing Supervisor and Operating Frequency Range
Since the controller is expected to operate with a variable switching
frequency over the line frequency half-cycle, typically spanning a
range of 22 – 123 kHz when operating in CCM, the controller also
features a timing supervisor function which monitors and limits the
maximum switch on-time and off-time as well as ensures a minimum
cycle on-time. Figure 9(a) shows the typical half-line frequency
profile of the device switching frequency as a function of input
voltage at peak load conditions. Figure 9(b) shows for a given line
condition of 115 VAC, the effect of EcoSmart™ on the switching
frequency as a function of load. The switching frequency is not a
function of boost choke inductance in CCM (continuous conduction
mode) operation.
V
E
Latch
RESET
I
S
dt
V
OFF
(V
OUT
-V
IN
)dt
Latch
SET
Gate
Drive (Q)
Maximum
ON-time
Minimum
OFF-time
Timing
Supervisor
Figure 5.
Idealized Converter Waveforms.
5
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Rev. A 06/15
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