74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Rev. 02 — 9 May 2008
Product data sheet
1. General description
The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and
the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data
appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch,
where the position of the switch is determined by the logic levels applied to input S. The
outputs are forced to a high-impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
1Y = OE
×
(1I1
×
S + 1I0
×
S)
2Y = OE
×
(2I1
×
S + 2I0
×
S)
3Y = OE
×
(3I1
×
S + 3I0
×
S)
4Y = OE
×
(4I1
×
S + 4I0
×
S)
The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has
non-inverting (true) outputs.
2. Features
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Non-inverting data path
Inputs accept voltages higher than V
CC
Input levels:
N
For 74AHC257: CMOS level
N
For 74AHCT257: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC257
74AHC257D
74AHC257PW
74AHCT257
74AHCT257D
74AHCT257PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT403-1
−40 °C
to +125
°C
−40 °C
to +125
°C
SO16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT403-1
Description
Version
Type number
4. Functional diagram
2
3
5
6
11
10
14
13
1I0 1I1
2I0 2I1
3I0 3I1
4I0 4I1
1 S
SELECTOR
15 OE
3-STATE MULTIPLEXER OUTPUTS
1Y
4
2Y
7
3Y
9
4Y
12
mgr280
Fig 1.
Functional diagram
74AHC_AHCT257_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
2 of 16
NXP Semiconductors
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
1
15
1
2
3
5
6
11
10
14
13
15
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
OE
mga835
G1
EN
S
1Y
4
2
3
5
1
1
MUX
4
2Y
7
7
6
11
9
10
3Y
9
4Y
12
14
12
13
001aad467
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
1I0
1Y
1I1
2I0
2Y
2I1
3I0
3Y
3I1
4I0
4Y
4I1
OE
S
001aad468
Fig 4.
Logic diagram
74AHC_AHCT257_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
3 of 16
NXP Semiconductors
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
5. Pinning information
5.1 Pinning
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
5
6
7
8
001aad499
16 V
CC
15 OE
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
9
3Y
257
Fig 5.
Pin configuration SO16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
3Y
3I1
3I0
4Y
4I1
4I0
OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
common data select input
data input from source 0
data input from source 1
multiplexer output
data input from source 0
data input from source 1
multiplexer output
ground (0 V)
multiplexer output
data input from source 1
data input from source 0
multiplexer output
data input from source 1
data input from source 0
output enable input (active LOW)
supply voltage
74AHC_AHCT257_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
4 of 16
NXP Semiconductors
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
6. Functional description
Table 3.
Control
OE
H
L
S
X
H
L
Function table
[1]
Input
nI0
X
X
X
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Output
nI1
X
L
H
X
X
nY
Z
L
H
L
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP16 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
74AHC_AHCT257_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
5 of 16
嵌入式系统
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