PSoC
®
4: PSoC 4200L Datasheet
Programmable System-on-Chip (PSoC
®
)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex
®
-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4200L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, program-
mable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion,
opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200L products will be fully
compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital
subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
■
■
■
■
Serial Communication
■
48 MHz ARM Cortex-M0 CPU with single-cycle multiply
Up to 256 kB of flash with Read Accelerator
Up to 32 kB of SRAM
DMA engine with 32 channels
Four opamps that operate in Deep Sleep mode at very low
current levels
All opamps have reconfigurable high current pin-drive,
high-bandwidth internal drive, ADC input buffering, and
Comparator modes with flexible connectivity allowing input
connections to any pin
Four current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Four independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I
2
C, SPI, or UART
functionality
USB Full-Speed device interface 12 Mbits/sec with Battery
Charger Detect capability
Two independent CAN blocks for industrial and automotive
networking
■
■
Programmable Analog
■
■
Timing and Pulse-Width Modulation
■
■
■
Eight 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
■
Programmable Digital
■
■
Up to 98 Programmable GPIOs
■
■
■
Eight programmable logic blocks, each with 8 Macrocells and
an 8-bit data path (called universal digital blocks or UDBs)
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
20-nA Stop Mode with GPIO pin wakeup
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFN
packages
Any of up to 94 GPIO pins can be CapSense, analog, or digital
Drive modes, strengths, and slew rates are programmable
Low Power 1.71 V to 5.5 V Operation
■
■
PSoC Creator Design Environment
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API component) for all
fixed-function and programmable peripherals
Capacitive Sensing
■
■
■
■
Two Cypress Capacitive Sigma-Delta (CSD) blocks provide
best-in-class SNR (>5:1) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
Industry-Standard Tool Compatibility
■
After schematic entry, development can be done with
ARM-based industry-standard development tools
Segment LCD Drive
■
■
LCD drive supported on any pin with up to a maximum of 64
outputs (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory
Cypress Semiconductor Corporation
Document Number: 001-91686 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 8, 2018
PSoC
®
4: PSoC 4200L Datasheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 4:
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐
AN79953:
Getting Started With PSoC 4
❐
AN88619:
PSoC 4 Hardware Design Considerations
❐
AN86439:
Using PSoC 4 GPIO Pins
❐
AN57821:
Mixed Signal Circuit Board Layout
❐
AN81623:
Digital Design Best Practices
❐
AN73854:
Introduction To Bootloaders
❐
AN89610:
ARM Cortex Code Optimization
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PSoC 4 functional block.
❐
Registers TRM
describes each of the PSoC 4 registers.
Development Kits:
❐
CY8CKIT-042,
PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
❐
CY8CKIT-046,
PSoC 4 L-Series Pioneer Kit, is an
easy-to-use and inexpensive development platform. This kit
includes connectors for Arduino™ compatible shields.
❐
CY8CKIT-049
is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐
CY8CKIT-001
is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The
MiniProg3
device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
3. Configure components using the configuration tools
1. Drag and drop component icons to build your hardware
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
1
2
3
5
Document Number: 001-91686 Rev. *I
Page 2 of 45
4
PSoC
®
4: PSoC 4200L Datasheet
Contents
PSoC 4200L Block Diagram............................................. 4
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Programmable Digital.................................................. 7
Fixed Function Digital.................................................. 8
GPIO ........................................................................... 9
SIO .............................................................................. 9
Special Function Peripherals....................................... 9
Pinouts ............................................................................ 10
Power............................................................................... 15
Unregulated External Supply..................................... 15
Regulated External Supply........................................ 15
Electrical Specifications ................................................ 16
Absolute Maximum Ratings....................................... 16
Device Level Specifications....................................... 16
Analog Peripherals .................................................... 20
Digital Peripherals ..................................................... 25
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Part Numbering Conventions ....................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
28
29
36
37
38
41
43
43
44
45
45
45
45
45
45
Document Number: 001-91686 Rev. *I
Page 3 of 45
PSoC
®
4: PSoC 4200L Datasheet
Figure 2. Block Diagram
PSoC 4200L
Architecture
32-bit
CPU Subsystem
SWD/ TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
256 KB
Read Accelerator
SRAM
32 KB
SRAM Controller
ROM
8 KB
ROM Controller
DataWire/
DMA
Initiator / MMIO
AHB- Lite
System Resources
Power
Sleep Control
WIC
POR
LVD
REF
BOD
PWRSYS
NVLatches
Clock
Clock Control
WDT
IMO
ILO
ECO 2 x PLL
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
System Interconnect (Multi Layer AHB )
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
Programmable
Digital
UDB
...
UDB
4x SCB-
I2C/SPI/UART
2x LP Comparator
IOSS GPIO
(13x ports)
2x Capsense
8x TCPWM
512B
2x CAN
LCD
x1
x8
SMX
CTBm
2 x OpAmp x2
Port Interface & Digital System Interconnect ( DSI)
CHG-DET
Power Modes
Active/ Sleep
Deep Sleep
Hibernate
High Speed I / O Matrix, 1x Programmable I/O
80 x GPIO, 14 x GPIO_ OVT , 2 x SIO
I/ O Subsystem
PSoC 4200L Block Diagram
The PSoC 4200L devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4200L devices. The SWD interface is fully compatible with
industry-standard third-party tools. The PSoC 4200L family
provides a level of security not possible with multi-chip appli-
cation solutions or with microcontrollers. This is due to its ability
to disable debug features, robust flash protection, and because
it allows customer-proprietary functionality to be implemented in
on-chip programmable blocks.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4200L with device security enabled may not be returned
for failure analysis. This is a trade-off the PSoC 4200L allows the
customer to make.
Document Number: 001-91686 Rev. *I
Page 4 of 45
FS-PHY
USB-FS
SAR ADC
(12-bit)
WCO
PSoC
®
4: PSoC 4200L Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4200L is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
execute a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC), which can wake the processor up
from the Deep Sleep mode allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4200L has four break-point
(address) comparators and two watchpoint (data) comparators.
Flash
The PSoC 4200L has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash block is designed to deliver 2 wait-state
(WS) access time at 48 MHz and with 1-WS access time at
24 MHz. The flash accelerator delivers 85% of single-cycle
SRAM access performance on average. Part of the flash module
can be used to emulate EEPROM operation if required.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
DMA
A DMA engine is provided that can do 32-bit transfers and has
chainable ping-pong descriptors.
Clock System
The PSoC 4200L clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no meta-stable conditions occur.
The clock system for the PSoC 4200L consists of a crystal oscil-
lator (4 to 33 MHz), a watch crystal oscillator (32 kHz), a
phase-locked loop (PLL), the IMO and the ILO internal oscil-
lators, and provision for an external clock.
Figure 3. PSoC 4200L MCU Clocking Architecture
IMO
clk_hf
clk_ext
PLL #1
ECO
(optional )
PLL #0
dsi_in[0]
dsi_in[1]
dsi_in[2]
dsi_in[3]
dsi_out[3:0]
ILO
clk_lf
WCO
The clk_hf signal can be divided down to generate synchronous
clocks for the UDBs, and the analog and digital peripherals.
There are a total of 16 clock dividers for the PSoC 4200L, each
with 16-bit divide capability; this allows 12 to be used for the
fixed-function blocks and four for the UDBs. The analog clock
leads the digital clocks to allow analog events to occur before
digital clock-related noise is generated. The 16-bit capability
allows a lot of flexibility in generating fine-grained frequency
values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4200L. It is trimmed during testing to achieve the specified
accuracy. Trim values are stored in nonvolatile latches (NVL).
Additional trim settings from flash can be used to compensate for
changes. The IMO default frequency is 24 MHz and it can be
adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power oscillator, nominally 32 kHz, which
is primarily used to generate clocks for peripheral operation in
Deep Sleep mode. ILO-driven counters can be calibrated to the
IMO to improve accuracy. Cypress provides a software
component, which does the calibration.
Crystal Oscillators and PLL
The PSoC 4200L clock subsystem also implements two oscil-
lators: high-frequency (4 to 33 MHz) and low-frequency (32-kHz
watch crystal) that can be used for precision timing applications.
The PLL can generate a 48-MHz output from the high-frequency
oscillator.
Page 5 of 45
System Resources
Power System
The power system is described in detail in the section
Power on
page 15.
It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low voltage detect (LVD)). The
PSoC 4200L operates with a single external supply over the
range of 1.71 to 5.5 V and has five different power modes, transi-
tions between which are managed by the power system. The
PSoC 4200L provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Document Number: 001-91686 Rev. *I
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
