Low Skew 1 to 10 Clock Buffer
74FCT3807S
DATASHEET
Description
The 74FCT3807S is a low skew, single input to ten output,
clock buffer. The 74FCT3807S has best in class additive
phase Jitter of sub 50 fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features
•
Low additive phase jitter RMS: 50fs
•
Low skew outputs (50ps)
•
Packaged in 20-pin TSSOP, SSOP, QSOP and VFQFPN
•
•
•
•
packages, Pb (lead) free
Operating voltages of 1.8V to 3.3V
Input/Output clock frequency up to 200 MHz
Advanced, low power CMOS process
Extended temperature range (-40°C to +105°C)
Block Diagram
Q0
Q1
Q2
Q3
Q4
ICLK
Q5
Q6
Q7
Q8
Q9
74FCT3807S REVISION A 03/18/15
1
©2015 Integrated Device Technology, Inc.
74FCT3807S DATASHEET
Pin Assignments
VDD
GND
17
Q9
Q8
ICLK
GND
Q0
VDD
Q1
GND
Q2
VDD
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Q9
Q8
GND
Q7
VDD
Q6
GND
Q5
Q4
VDD
Q1
GND
Q0
2
3
4
5
20
19
18
ICLK
1
16
15
14
Q7
VDD
Q6
GND
Q5
Q4
13
12
11
10
EPAD
6
7
8
9
GND
20-pin TSSOP/SSOP/QSOP
20-pin VFQFPN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
ICLK
GND
Q0
VDD
Q1
GND
Q2
VDD
Q3
GND
Q4
Q5
GND
Q6
VDD
Q7
GND
Q8
Q9
VDD
Pin
Type
Input
Power
Output
Power
Output
Power
Output
Power
Output
Power
Output
Output
Power
Output
Power
Output
Power
Output
Output
Power
Clock input.
Connect to ground.
Clock output 0.
Connect to +1.8V, +2.5 V, or +3.3 V.
Clock output 1.
Connect to ground.
Clock Output 2.
Connect to +1.8V, +2.5 V, or +3.3 V.
Clock Output 3.
Connect to ground.
Clock Output 4.
Clock Output 5.
Connect to ground.
Clock Output 6.
Connect to +1.8V, +2.5 V, or +3.3 V.
Clock Output 7.
Connect to ground.
Clock Output 8.
Clock Output 9.
Connect to +1.8V, +2.5 V, or +3.3 V.
Pin Description
LOW SKEW 1 TO 10 CLOCK BUFFER
2
GND
VDD
Q2
Q3
REVISION A 03/18/15
74FCT3807S DATASHEET
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be
connected between VDD pins and GND pins, as close to the device as possible. A 33
series terminating resistor may be used
on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 74FCT3807S is capable of, careful attention must be paid to board layout. Essentially,
all ten outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew
will be degraded. For example, using a 30
series termination on one output (with 33
on the others) will cause at least 15 ps
of skew.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 74FCT3807S. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Item
Supply Voltage, VDD
Outputs
ICLK
Ambient Operating Temperature (extended)
Storage Temperature
Junction Temperature
Soldering Temperature
3.465V
-0.5 V to VDD+0.5 V
3.465V
-40° to +105°C
-65° to +150°C
125°C
260°C
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (extended)
Power Supply Voltage (measured in respect to GND)
Min.
-40
+1.71
Typ.
Max.
+105
+3.465
Units
C
V
REVISION A 03/18/15
3
LOW SKEW 1 TO 10 CLOCK BUFFER
74FCT3807S DATASHEET
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD=1.8V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
I
OH
= -10 mA
I
OL
= 10 mA
No load, 135 MHz
ICLK
Min.
1.71
0.7xVDD
1.3
Typ.
Max.
1.89
VDD
0.3xVDD
0.35
Units
V
V
V
V
V
mA
pF
35
17
5
Notes: 1. Nominal switching threshold is VDD/2
VDD=2.5 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
I
OH
= -16 mA
I
OL
= 16 mA
No load, 135 MHz
ICLK
Min.
2.375
0.7xVDD
1.8
Typ.
Max.
2.625
VDD
0.3xVDD
0.5
Units
V
V
V
V
V
mA
pF
45
17
5
VDD=3.3 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
I
OH
= -25 mA
I
OL
= 25 mA
No load, 135 MHz
ICLK
Min.
3.15
0.7xVDD
2.2
Typ.
Max.
3.45
VDD
0.3xVDD
0.7
Units
V
V
V
V
V
mA
pF
55
17
5
LOW SKEW 1 TO 10 CLOCK BUFFER
4
REVISION A 03/18/15
74FCT3807S DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
t
START-UP
t
OR
t
OF
0.36 to 1.44 V, C
L
=5 pF
1.44 to 0.36 V, C
L
=5 pF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
50
1.5
Symbol
Conditions
Min.
0
Typ.
1.4
1.4
2.5
Max.
200
1.9
1.9
4
0.05
65
200
2
Units
MHz
ns
ns
ns
ps
ps
ps
ms
VDD = 2.5 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
t
START-UP
t
OR
t
OF
0.5 to 2.0 V, C
L
=5 pF
2.0 to 0.5 V, C
L
=5 pF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
50
1.8
Symbol
Conditions
Min.
0
Typ.
1.0
1.0
2.5
Max.
200
1.5
1.5
4.5
0.05
65
200
2
Units
MHz
ns
ns
ns
ps
ps
ps
ms
VDD = 3.3 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
t
START-UP
t
OR
t
OF
0.66 to 2.64 V, C
L
=5 pF
2.64 to 0.66 V, C
L
=5 pF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
50
1.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
2.5
Max.
200
1.0
1.0
4
0.05
65
200
2
Units
MHz
ns
ns
ns
ps
ps
ps
ms
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
REVISION A 03/18/15
5
LOW SKEW 1 TO 10 CLOCK BUFFER
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