74LV138DB: 产品描述Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV; 产品类别逻辑逻辑; 文件大小98KB，共18页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LV138DB概述

Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV

74LV138DB规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	SSOP
包装说明	SSOP, SSOP16,.3
针数	16
Reach Compliance Code	compliant
ECCN代码	EAR99
其他特性	3 ENABLE INPUTS
系列	LV/LV-A/LVX/H
输入调节	STANDARD
JESD-30 代码	R-PDSO-G16
JESD-609代码	e4
长度	6.2 mm
负载电容（CL）	50 pF
逻辑集成电路类型	OTHER DECODER/DRIVER
最大I（ol）	0.006 A
湿度敏感等级	1
功能数量	1
端子数量	16
最高工作温度	125 °C
最低工作温度	-40 °C
输出极性	INVERTED
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装等效代码	SSOP16,.3
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260
电源	3.3 V
Prop。Delay @ Nom-Sup	32 ns
传播延迟（tpd）	32 ns
认证状态	Not Qualified
座面最大高度	2 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	1 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	AUTOMOTIVE
端子面层	NICKEL PALLADIUM GOLD
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	5.3 mm
Base Number Matches	1

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74LV138

3-to-8 line decoder/demultiplexer; inverting

Rev. 03 — 15 November 2007

Product data sheet

1. General description

The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC138 and 74HCT138.

The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted

address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive

active LOW outputs (Y0 to Y7).

There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).

Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the device to a 1-of-32

(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The

74LV138 can be used as an eight output demultiplexer by using one of the active LOW

enable inputs as the data input and the remaining enable inputs as strobes. Unused

enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

2. Features

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

°C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

°C

Demultiplexing capability

Multiple input enable for easy expansion

Ideal for memory chip select decoding

Active LOW mutually exclusive outputs

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

74LV138DB相似产品对比

	74LV138DB	74LV138D-T	74LV138PW-T	74LV138DB-T	74LV138N
描述	Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV	Encoders, Decoders, Multiplexers u0026 Demultiplexers 3 TO 8 LINE DECODER DEMUX INV	Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV	Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV	Encoders, Decoders, Multiplexers & Demultiplexers 3 TO 8 LINE DECODER DEMUX INV
是否Rohs认证	符合	符合	符合	符合	符合
厂商名称	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	SSOP	SOIC	TSSOP	SSOP	DIP
包装说明	SSOP, SSOP16,.3	SOP, SOP16,.25	TSSOP,	SSOP,	DIP, DIP16,.3
针数	16	16	16	16	16
Reach Compliance Code	compliant	unknown	unknown	unknown	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99
其他特性	3 ENABLE INPUTS	3 ENABLE INPUTS	3 ENABLE INPUTS	3 ENABLE INPUTS	3 ENABLE INPUTS
系列	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
输入调节	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 代码	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16
JESD-609代码	e4	e4	e4	e4	e4
长度	6.2 mm	9.9 mm	5 mm	6.2 mm	19.025 mm
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF
功能数量	1	1	1	1	1
端子数量	16	16	16	16	16
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出极性	INVERTED	INVERTED	INVERTED	INVERTED	INVERTED
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SOP	TSSOP	SSOP	DIP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	IN-LINE
峰值回流温度（摄氏度）	260	260	260	260	NOT SPECIFIED
传播延迟（tpd）	32 ns	32 ns	32 ns	32 ns	32 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2 mm	1.75 mm	1.1 mm	2 mm	4.2 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	1 V	1 V	1 V	1 V	1 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE
端子节距	0.65 mm	1.27 mm	0.65 mm	0.65 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	NOT SPECIFIED
宽度	5.3 mm	3.9 mm	4.4 mm	5.3 mm	7.62 mm
Base Number Matches	1	1	1	1	1
逻辑集成电路类型	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	-	-	OTHER DECODER/DRIVER
最大I（ol）	0.006 A	0.006 A	-	-	0.006 A
湿度敏感等级	1	1	1	1	-
封装等效代码	SSOP16,.3	SOP16,.25	-	-	DIP16,.3
电源	3.3 V	3.3 V	-	-	3.3 V
Prop。Delay @ Nom-Sup	32 ns	32 ns	-	-	32 ns
Source Url Status Check Date	-	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00

74LV138DB

74LV138DB在线购买

74LV138DB概述

74LV138DB规格参数

文档预览

74LV138DB相似产品对比

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