notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. A
06/01/09
1
IS43R16800CC
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION:
A0-A11
A0-A8
BA0, BA1
DQ0 – DQ15
CLK,
CLK
CKE
CS
CAS
RAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe
Command
WE
LDM, UDM
LDQS, UDQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
2
Integrated Silicon Solution, Inc.
Rev. A
06/01/09
Zentel Electronics Corporation
I
IS43R16800CC
I
PIN FUNCTION
SYMBOL
Preliminary
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
TYPE
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-8.
A10 is also used to indicate precharge
option. When A10 is high at a read / write,
an auto precharge is
performed. When A10 is high at a precharge command,
all banks are
precharged.
CLK, /CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
D
DQ0-15
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
V
DDQ,
and
V
SSQ
are supplied to the Output Buffers only.
Input / Output
D
UDQS, LDQS
Input / Output
D
UDM, LDM
Input
V
DD
,
V
SS
V
DDQ,
V
SSQ
Power Supply
Power Supply
Input
Vref
SSTL_2 reference voltage.
Integrated Silicon Solution, Inc.
Rev.
A
06/01/09
DDR SDRAM (Rev.1.1)
3
IS43R16800CC
DQ 0 - 15
UDQS, LD QS
BLOCK DIAGRAM x16
DLL
I/O B uffer
DQ S Buffer
Memory
Array
Bank #0
Memory
Array
Ba nk #1
Memory
Array
Ba nk #2
Memory
Array
Ba nk #3
Mode Re gister
Control C ircu itry
Addres s B uffer
Cl ock B uffer
A0-11
BA 0,1
CLK
/CLK
CKE
Control Signal B uffer
/CS /RAS /CAS
/WE
UDM ,
LD M
4
Integrated Silicon Solution, Inc.
Rev.
A
06/01/09
Zentel Electronics Corporation
IS43R16800CC
I
Preliminary
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
ISSI's
128-Mbit
DDR SDRAM
provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
BASIC FUNCTIONS
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,
READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA
).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
PCB设计
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