DATASHEET
PLL BUILDING BLOCK
Description
The ICS663 is a low cost Phase-Locked Loop (PLL)
designed for clock synthesis and synchronization. Included
on the chip are the phase detector, charge pump, Voltage
Controlled Oscillator (VCO) and an output buffer. Through
the use of external reference and VCO dividers
(implemented with the ICS674-01, for example), the user
can easily configure the device to lock to a wide variety of
input frequencies.
The phase detector and VCO functions of the device can
also be used independently. This enables the configuration
of other PLL circuits. For example, the ICS663 phase
detector can be used to control a VCXO circuit such as the
MK3754.
For applications requiring Power Down or Output Enable
features, please refer to the ICS673-01.
ICS663
Features
•
Packaged in 8-pin SOIC (Pb free)
•
Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to
•
120 MHz (5 V)
External PLL loop filter enables configuration for a wide
range of input frequencies
Hsync, for example)
•
Ability to accept an input clock in the kHz range (video
•
•
•
•
25 mA output drive capability at TTL levels
Lower power CMOS process
+3.3 V ±5% or +5 V ±10% operating voltage
Used along with the ICS674-01, forms a complete PLL
circuit
independently for other PLL configurations
•
Phase detector and VCO blocks can be used
•
Industrial temperature version available
•
For better jitter performance, use the MK1575
Block Diagram
LF
LFR
VDD
I
cp
C lock Input
R E FIN
P hase/
Frequency
D etector
UP
FB IN
VCO
DOW N
1
MUX
4
0
2
C LK
I
cp
SEL
External Feedback D ivider
(such as the IC S674-01)
IDT™ / ICS™
PLL BUILDING BLOCK
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ICS663
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ICS663
PLL BUILDING BLOCK
PLL BUILDING BLOCK
Pin Assignment
VCO Post Divide Select Table
SEL
VCO Post
Divide
8
2
FBIN
VDD
GND
LF
1
2
3
4
8
7
6
5
REFIN
CLK
SEL
LFR
0
1
0 = connect pin directly to ground
1 = connect pin directly to VDD
8 Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
Pin
Name
FBIN
VDD
GND
LF
Pin
Type
Input
Power
Power
Input
Pin Description
Feedback clock input. Connect the output of the feedback divider to
this pin. Falling edge triggered.
VDD. Connect to +3.3 V or +5 V.
Connect to ground.
Loop filter connection (refer to Figure 1 on Page 5).
When using the phase detector block only, this pin serves as the
charge pump output.
When using the VCO block only, this pin serves as VCO input control
voltage.
Loop filter return (refer to Figure 1 on Page 5).
Select pin for VCO post divide, as per above table.
Clock output.
Reference clock input. Connect the input clock to this pin. Falling edge
triggered.
5
6
7
8
LFR
SEL
CLK
REFIN
Input
Input
Output
Input
IDT™ / ICS™
PLL BUILDING BLOCK
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ICS663
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PLL BUILDING BLOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS663. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Industrial Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70° C
-40 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.13
Typ.
Max.
+85
+5.5
Units
°
C
V
DC Electrical Characteristics
VDD=3.3 V ±5% or 5.0 V ±10%,
Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Logic Input High Voltage
Logic Input Low Voltage
LF Input Voltage Range
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS
level
Operating Supply Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
I
V
OH
V
OL
V
OH
IDD
I
OS
C
I
Conditions
REFIN, FBIN,
SEL
REFIN, FBIN,
SEL
Min.
3.13
2
Typ.
Max.
5.5
Units
V
V
0.8
0
VDD
0.4
VDD-0.4
15
±100
5
V
V
V
V
I
OH
= -25 mA
I
OL
= 25 mA
I
OH
= -8 mA
VDD = 5.0 V,
No load, 40 MHz
CLK
SEL
2.4
mA
mA
pF
IDT™ / ICS™
PLL BUILDING BLOCK
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ICS663
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ICS663
PLL BUILDING BLOCK
PLL BUILDING BLOCK
AC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Symbol
f
CLK
f
REF
t
OR
t
OF
t
DC
t
J
K
O
I
cp
Conditions
SEL = 1
SEL = 0
Min.
1
0.25
Note 1
Typ.
Max. Units
100
25
8
MHz
MHz
MHz
ns
ns
%
ps
MHz/V
µA
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
40
1.2
0.75
50
250
200
2.5
2
1.5
60
VDD = 5.0 V ±10%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Symbol
f
CLK
f
REF
t
OR
t
OF
t
DC
t
J
K
O
I
cp
Conditions
SEL = 1
SEL = 0
Min.
1
0.25
Note 1
Typ.
Max. Units
120
30
8
MHz
MHz
MHz
ns
ns
%
ps
MHz/V
µA
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
45
0.5
0.5
50
150
200
2.5
1
1
55
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
PLL BUILDING BLOCK
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ICS663
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PLL BUILDING BLOCK
External Components
The ICS663 requires a minimum number of external
components for proper operation. A decoupling capacitor of
0.01µF should be connected between VDD and GND as
close to the ICS663 as possible. A series termination
resistor of 33Ω may be used at the clock output.
Special considerations must be made in choosing loop
components C
1
and C
2
:
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason, DO
NOT use any type of polarized or electrolytic capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is less
than 1 kHz. For this reason, ceramic capacitors should have
C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and
X7R. These and some other ceramics have piezoelectric
properties that convert mechanical vibration into voltage
noise that interferes with VCXO operation.
For larger loop capacitor values such as 0.1µF or 1µF, PPS
film types made by Panasonic, or metal poly types made by
Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or IDT
Applications.
Avoiding PLL Lockup
In some applications, the ICS663 can “lock up” at the
maximum VCO frequency. The way to avoid this problem is
to use an external divider that always operates correctly
regardless of the CLK output frequency. The CLK output
frequency may be up to 2x the maximum Output Clock
Frequency listed in the AC Electrical Characteristics above
when the device is in an unlocked condition. Make sure that
the external divider can operate up to this frequency.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes an
integrated VCO with a wide operating range. The device
uses external PLL loop filter components which through
proper configuration allow for low input clock reference
frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling edges of
the clocks inputted to FBIN and REFIN. It then generates an
error signal to the charge pump, which produces a charge
proportional to this error. The external loop filter integrates
this charge, producing a voltage that then controls the
frequency of the VCO. This process continues until the
edges of FBIN are aligned with the edges of the REFIN
clock, at which point the output frequency will be locked to
the input frequency.
Figure 1. Example Configuration
-- Generating a 20 MHz clock from a 200 kHz reference
+3.3 or 5 V
C
2
0.01
µ
F
R
Z
VDD
200 kH z
C
1
LFR
SEL
LF
R E FIN
IC S 6 6 3
C LK
20 M H z
F B IN
GND
200 kH z
100
D igital D ivider such as
IC S 674-01
IDT™ / ICS™
PLL BUILDING BLOCK
5
ICS663
REV E 012006
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