电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74LCX540WM_Q

产品描述Buffers & Line Drivers Octal Buff/Line Drv
产品类别半导体    逻辑   
文件大小746KB,共15页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
下载文档 详细参数 选型对比 全文预览

74LCX540WM_Q在线购买

供应商 器件名称 价格 最低购买 库存  
74LCX540WM_Q - - 点击查看 点击购买

74LCX540WM_Q概述

Buffers & Line Drivers Octal Buff/Line Drv

74LCX540WM_Q规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
Fairchild
产品种类
Product Category
Buffers & Line Drivers
RoHSN
Number of Input Lines8 Input
Number of Output Lines8 Output
PolarityInverting
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
SOIC-20
系列
Packaging
Tube
FunctionBuffer/Line Driver
高度
Height
2.35 mm (Max)
长度
Length
13 mm (Max)
输出类型
Output Type
3-State
Quiescent Current10 uA
技术
Technology
CMOS
宽度
Width
7.6 mm (Max)
Logic FamilyLCX
Logic TypeBuffer and Driver
Number of Channels8
Supply Current - Max10 uA
High Level Output Current- 24 mA
Input Signal TypeSingle-Ended
Low Level Output Current24 mA
NumOfPackaging1
工作电源电压
Operating Supply Voltage
2.3 V to 3.6 V
传播延迟时间
Propagation Delay Time
7.5 ns at 2.7 V, 6.5 ns at 3.3 V
单位重量
Unit Weight
0.028254 oz

文档预览

下载PDF文档
74LCX540 — Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
December 2013
74LCX540
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
Features
5V tolerant input and outputs
2.3V–3.6V V
CC
specifications provided
6.5ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
(1)
Implements p
roprietary
noise/ EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance
General Description
The LCX540 is an octal buffer/line driver designed to be
employed as a memory and address driver, clock driver
and bus oriented transmitter/receiver.
This device is similar in function to the LCX240 while
providing flow-through architecture (inputs on opposite
side from outputs). This pinout arrangement makes this
device especially useful as an output port for micropro-
cessors, allowing ease of layout and greater PC board
density.
The LCX540 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V
signal environment. The LCX540 is fabricated with an
advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipa-
tion.
– Human body model
>
2000V
– Machine model
>
200V
Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to V
CC
through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Order Number
74LCX540WM
74LCX540SJ
74LCX540BQX
(2)
74LCX540MSA
74LCX540MTC
Package
Number
M20B
M20D
MLP20B
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX540 Rev. 1.7.1
www.fairchildsemi.com

74LCX540WM_Q相似产品对比

74LCX540WM_Q 74LCX540MSA
描述 Buffers & Line Drivers Octal Buff/Line Drv Buffers & Line Drivers Octal Buff/Line Drv
如何对多个IO口同时赋值?
请问,对于不同的IO,比如GPIOA1,A2,A3 ,B1,B2,B3,C1,C2 可不可以用结构体对这非连续的八个IO口写到一组里面,然后向对这一组IO口的值同时赋值?或者对这一组IO口的值同时读取值?多谢!...
玻璃之城2046 stm32/stm8
EEWORLD大学堂----Miz702 zynq视频初阶教程(米联客)
Miz702 zynq视频初阶教程(米联客):https://training.eeworld.com.cn/course/5654米联客miz702视频for fresh man,讲述开发环境,ZYNQ GPIO、ADC、DDR、AXI等内容...
木犯001号 FPGA/CPLD
raw-os 2.005 版本发布
raw-os 2.005 版本发布 下载地址为: http://www.raw-os.org/download.html 新增加的特性使用请参考: Raw-OS 2.005 VS 2015平台移植版 ...
jorya_txj 嵌入式系统
msp430f5529中断笔记
定义中断服务程序 #pragma vector=PORT1_VECTOR//P1口中断向量 __interrupt void Port_1(void)//声明中断服务程序,名为Port_1 { ...//中断服务程序 } 定时器中断应用例程 #include ......
Aguilera 微控制器 MCU
求助好心人帮忙申请个芯片数据手册
求助申请芯片MAX3601,由于学校的原因,芯片公司各种封锁,连个数据手册都不给。,哪位好心人帮忙申请下。。...
panchhunhui FPGA/CPLD
给新入职的坛友一定建议
多主动,多奉献。多积累,多沉淀。不要看眼前得失,要看长远!...
eeleader 工作这点儿事

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1547  754  295  2469  1490  2  6  56  22  50 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved