Data Sheet, Rev. 1.0, May 2008
BTM7810K
TrilithIC
Automotive Power
BTM7810K
Table of Contents
Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
2
2.1
2.2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
5.1
5.2
5.3
5.4
6
7
8
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Circuit Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
8
8
8
8
8
9
10
10
11
11
12
Application Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Sheet
2
Rev. 1.0, 2008-05-15
TrilithIC
BTM7810K
1
Features
•
•
•
•
Overview
Quad D-MOS switch
Free configurable as bridge or quad-switch
Optimized for DC motor management applications
Low
R
DS ON
High side: 26 mΩ typ. @ 25°C, 65 mΩ max. @ 110°C
Low side: 14mΩ typ. @ 25°C, 28 mΩ max. @ 110°C
Maximum peak current: typ. 42 A @ 25
°C
Very low quiescent current: typ. 4
μA
@ 25
°C
Thermally optimized power package
Operates up to 40 V
Load and GND-short-circuit-protection
Overtemperature shut down with hysteresis
Undervoltage detection with hysteresis
Open load detection in OFF mode
Status flag for overtemperature
Internal clamp diodes
Isolated sources for external current sensing
Green Product (RoHS compliant)
AEC Qualified
•
•
•
•
•
•
•
•
•
•
•
•
•
PG-TO263-15-1
Description
The
BTM7810K
is part of the
TrilithIC
family containing three dies in one package: One double high-side switch
and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated lead frames.
The sources are connected to individual pins, so the
BTM7810K
can be used in H-bridge- as well as in any other
configuration. The double high-side switch is manufactured in SMART SIPMOS
®
technology which combines low
R
DS ON
vertical DMOS power stages with CMOS circuitry for control, protection and diagnosis. To achieve low
R
DS ON
and fast switching performance, the low-side switches are manufactured in S-FET logic level technology.
Type
BTM7810K
Data Sheet
Package
PG-TO263-15-1
3
Marking
BTM7810K
Rev. 1.0, 2008-05-15
BTM7810K
Description
2
2.1
Pin Configuration
Pin Assignment
Molding
Compound
NC
SL1
IL1
NC
IH1
ST1
SH1
DHVS
GND
IH2
ST2
SH2
IL2
SL2
NC
1
Heat-Slug 1
2
18
3
4
5
Heat-Slug 2
6
7
8
9
10
11
12
Heat-Slug 3
13
16
14
15
DL2
17
DHVS
DL1
Figure 1
Pin Assignment BTM7810K (Top View)
Data Sheet
4
Rev. 1.0, 2008-05-15
BTM7810K
Description
Table 1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Definitions and Functions
Symbol Function
NC
SL1
IL1
NC
IH1
ST1
SH1
DHVS
GND
IH2
ST2
SH2
IL2
SL2
NC
DL2
DHVS
DL1
Not connected
Source of low-side switch 1
Analog input of low-side switch 1
Not connected
Digital input of high-side switch 1
Status of high-side switch 1; open Drain output
Source of high-side switch 1
Drain of high-side switches and power supply voltage
Ground of high-side switches
Digital input of high-side switch 2
Status of high-side switch 2; open Drain output
Source of high-side switch 2
Analog input of low-side switch 2
Source of low-side switch 2
Not connected
Drain of low-side switch 2
Heat-Slug 3
Drain of high-side switches and power supply voltage
Heat-Slug 2
Drain of low-side switch 1
Heat-Slug 1
Pins written in
bold type
need power wiring.
Data Sheet
5
Rev. 1.0, 2008-05-15
FPGA/CPLD
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