W173
Tape Drive Frequency Timing Generator
Features
• Four derived outputs at frequencies specified by
Hewlett Packard Computer Peripherals Bristol/Boise
(CPB)
• Less than ±250 ps cycle-to-cycle jitter
(13.2 MHz clock excluded derated to ±400 ps)
• Less than ±350 ps absolute jitter
• Supports 3.3V operation
• TTL compatible logic: V
IL
= 0.8V max., V
IH
= 2.0V min.,
V
OL
= 0.4V max., and V
OH
= 2.4V min.
• OE pin has internal pull-up
• 45/55% duty cycle on all outputs
• 15 output drivers
• Accepts 26.5625 MHz input reference
• Built-in crystal oscillator circuit. Capacitive load
presented to the crystal is approximately 14 pF
• Outputs designed to drive 30 pF loads
• Available in 16-pin SOIC package
Functional Description
The W173 has been defined to meet the timing signal require-
ments for Hewlett Packard CPB tape drive system.
S
Block Diagram
Pin Configuration
REFIN
XTAL
OSC
VDD
X1
X2
GND
OE
13.2 MHz
VDD
50MHZ
6.6 MHz
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
6.6MHZ
GND
13.2MHZ
VDD
GND
10MHZ
VDD
PLL 1
50 MHz
PLL 2
10 MHz
OE
..........Document #: 38-07313 Rev. *B Page Page 1 of 5 of 5
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
W173
Pin Definitions
Pin Name
OE
13.2MHZ
6.6MHZ
10MHZ
50MHZ
X1
[1]
Pin No.
5
13
15
10
7
2
Pin Type
I
O
O
O
O
I
Pin Description
Output Enable:
When LOW, this input signal puts all outputs into a high-impedance
state.
Clock Output:
Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 13.2 MHz.
Clock Output:
Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 6.6 MHz.
Clock Output:
Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 10.0 MHz.
Clock Output:
Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 50.0 MHz.
External Crystal Connection:
This pin has dual functions. It can be used as an
external 26.5625 MHz crystal connection or as an external reference frequency
input.
External Crystal Connection:
An input connection for an external 26.5625 MHz
crystal. If using an external reference, this pin must be left unconnected.
Power Supply Connections:
Connect both V
DD
pins to the same voltage, either
3.3V or 5.0V. Each V
DD
pin should have a decoupling capacitor (such as 0.1 µF)
placed as close to the pin as possible.
Ground Connections:
Connect all ground pins to the common system ground
plane.
X2
VDD
3
1, 6, 9, 12, 16
O
P
GND
4, 8, 11, 14
G
Note:
1. All inputs, except X1 or X2, have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.
......... Document #: 38-07313 Rev. *B Page Page 2 of 5 of 5
W173
Power Supply Connections
The recommended single voltage power supply configuration
for the W173 is shown schematically in
Figure 1.
These recom-
mendations should be followed to both ensure adequate
device performance and to control EMI. The major consider-
ations can be summarized as follows:
1. Decoupling Capacitor—A 0.1-µF decoupling capacitor
should be used for each V
DD
pin to minimize crosstalk be-
tween output frequencies. The trace to the V
DD
pin and to
the ground via should be as short as possible.
2. Ferrite Bead (FB)—A common supply connection should
be used for all W173 V
DD
pins. A ferrite bead should be
used on this common supply as shown to remove high
frequency system noise.
3. 22-µF Supply Filter Capacitor—The 22-µF capacitor filters
low frequency supply noise that may produce clock output
jitter. Depending on the particular application, this capacitor
may not be required; its use should be considered optional.
Mounting pads should be implemented in PCB layout. Use
of this capacitor in production should be determined upon
prototype evaluation.
4. PCB power supply traces should be at least 20 mils wide to
assure adequate trade impedance recommend Power
Supply Schematic–Single Voltage Supply Operation.
Ground Connections
All ground connections should be made to the main system
ground plane. These connections should be as short as
possible. No cuts should be made in the ground plane around
the clock device since this can increase system EMI and
reduce clock performance.
Clock Output Lines
1. The clock line width should be set to provide a 60 trace
impedance. This width will vary depending on the PCB ma-
terial; the PCB supplier can suggest what width to use for
a 60 clock line. In general, an 8-mil trace will provide a
60impedance on a multi-level board.
2. The series termination resistor (sometimes called “damping
resistor”) must be placed in series with the clock line as
close to the clock output as possible (within one inch).
3. Assume an output resistance from the W173 of 40,
choose series resistors appropriate to the number of driven
traces.
System VDD
FB
22 µF
C1
VDD
0.1 µF
X1
X2
GND
OE
VDD
0.1 µF
50MHz
GND
1
2
3
16
15
14
VDD
6.6MHz
GND
13.2MHz
VDD
GND
10MHz
VDD
0.1 µF
W173
4
5
6
7
8
13
12
11
10
9
0.1 µF
0.1 µF
Figure 1. Test Circuit
......... Document #: 38-07313 Rev. *B Page Page 3 of 5 of 5
W173
Absolute Maximum Ratings
[2]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Table 1:
Parameter
V
DD
, V
IN
T
STG
T
B
T
A
Description
Voltage on Any Pin with Respect to GND
Storage Temperature
Ambient Temperature under Bias
Operating Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
°C
°C
°C
DC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 3.3V±5%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
R
P
C
I
L
I
C
L
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Input Pull-up Resistor
Input Capacitance
Input Inductance
XTAL Load Capacitance
V
IN
= 0V
Except X1 and X2
Except X1 and X2
Total load to crystal
12
500
6
7
Test Condition
Note: CLK output = 50.0 MHz
output loaded
V
CC
= 5.0V
V
CC
= 5.0V
I
OL
= 1 mA
I
OH
= –1 mA
3.1
10
10
2.0
50
Min.
Typ.
Max.
40
0.8
Unit
mA
V
V
mV
V
µA
µA
k
pF
nH
pF
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
CC
= 3.3V±5%
[3]
Parameter
Clock Outputs
t
JC
Z
O
d
T
t
R
t
F
t
PU
f
A
Output Clock Jitter, Cycle-to-Cycle Excluding 13.2-MHz output
Output Buffer Impedance
Output Duty Cycle
Rise Time
Fall Time
Long Term Output Frequency
Stability
Between 0.4V and 2.4V
Between 2.4V and 0.4V
Over V
CC
and T
A
range
45
0.8
0.8
±175
40
50
1.5
1.5
1.5
55
4.0
4.0
3.0
0.01
±250
ps
W
%
V/ns
V/ns
ms
%
Description
Test Condition
Min.
Typ.
Max.
Unit
Stabilization Time from Power-Up To within 0.1% of final frequency
Note:
2.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. All AC tests are performed using the circuit shown in
Figure 1
to simulate typical system load conditions. Measurements are taken at the load. Threshold voltage
for timing measurements is 1.5V.
......... Document #: 38-07313 Rev. *B Page Page 4 of 5 of 5
W173
Ordering Information
Ordering Code
W173G
W173GT
Lead Free
CYW173SXC
CYW173SXCT
16-pin SOIC (150 mil)
16-pin SOIC (150 mil) - Tape and Reel
16-pin SOIC (150 mil)
16-pin SOIC (150 mil) - Tape and Reel
Package Type
Package Drawing and Dimensions
16 Lead (150 Mil) SOIC
8
1
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.010[0.254]
0.016[0.406]
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
......... Document #: 38-07313 Rev. *B Page Page 5 of 5 of 5
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