logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C34 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I
2
C slave, master, and multimaster;
FS USB; and Full CAN 2.0b.
Page 3 of 143
Document Number: 001-57331 Rev. *G
PSoC
®
3: CY8C34
Automotive Family Datasheet
For more details on the peripherals see the
“Example
Peripherals”
section on page 40 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 40 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
Analog-to-digital converter (ADC)
Digital-to-analog converters (DACs)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features
[4]
:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±2 LSB
DNL less than ±1 LSB
SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
Two high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths. In addition
to the ADC, and DACs, the analog subsystem provides multiple:
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the
“Analog Subsystem”
section on page 51 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive
[5]
, CapSense
[6]
, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow V
OH
to be set independently of Vddio when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I
2
C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the
“I/O System and Routing”
section on
page 33 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the clock base for the
system, and has 1-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 50 MHz from the IMO, external crystal,
or external reference clock.
Notes
4. Refer
Electrical Specifications
on page 65 for the detailed ADC specification across entire voltage range and temperature
5. This feature on select devices only. See
Ordering Information
on page 133 for details.
6. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-57331 Rev. *G
Page 4 of 143
PSoC
®
3: CY8C34
Automotive Family Datasheet
It also contains a separate, very low-power internal low-speed
oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz
external watch crystal is also supported for use in real-time
clock (RTC) applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C34 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%,
or directly from a wide range of battery types.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode, the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 29 of this data sheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces you can debug or program the
PSoC with a variety of hardware solutions from Cypress or third
party vendors. PSoC supports on-chip break points and 4-KB
instruction and data race memory for debug. Details of the
programming, test, and debugging interfaces are discussed in
the
“Programming, Debug Interfaces, Resources”
section on
page 60 of this data sheet.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in
Figure 2-3
through
Figure 2-4
show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA
[7]
total to its associated
I/O pins, as shown in
Figure 2-1.
Figure 2-1. VDDIO Current Limit
I
DDIO X
= 100 mA
V
DDIO X
I/O Pins
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA
[7]
total,
as shown in
Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
V
DDIO X
I/O Pins
PSoC
V
SSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA
[7]
total. The set
of I/O pins associated with VDDIO1 plus VDDIO3 may sink up to
a total of 100 mA.
Note
7. The 100 mA source/ sink current per Vddio is valid only for temperature range of –40 °C to +85 °C. For extended temperature range of –40 °C to +125 °C, the maximum
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