Programmable System-on-Chip (PSoC )
Programmable System-on-Chip (PSoC
®
)
Automotive PSoC
®
4: PSoC 4000
Family Datasheet
®
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. The PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a
combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense)
with best-in-class performance, and general-purpose analog. PSoC 4000 products will be fully upward compatible with members of
the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
■
■
■
Up to 20 Programmable GPIO Pins
■
■
■
24-pin QFN and 16-pin SOIC packages
GPIO pins on Ports 0, 1, and 2 can be CapSense or have other
functions
Drive modes, strengths, and slew rates are programmable
16-MHz ARM Cortex-M0 CPU
Up to 16 KB of flash with Read Accelerator
Up to 2 KB of SRAM
Programmable Analog
■
■
Temperature Ranges
■
■
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications
One low-power comparator with internal reference
A Grade: –40 °C to +85 °C
S-Grade: –40°C to +105 °C
Automotive Electronics Council (AEC) Q100 qualified
Low Power 1.71-V to 5.5-V operation
■
Deep Sleep mode with wake-up on interrupt and I
2
C address
detect
PSoC Creator Design Environment
■
Capacitive Sensing
■
■
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
■
Industry-Standard Tool Compatibility
■
After schematic entry, development can be done with
ARM-based industry-standard development tools
Serial Communication
■
Multi-master I
2
C block with the ability to do address matching
during Deep Sleep and generate a wake-up on match
Timing and Pulse-Width Modulation
■
■
■
One 16-bit Timer/Counter/Pulse-Width Modulator (TCPWM)
block
Center-aligned, Edge, and Pseudo-Random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Cypress Semiconductor Corporation
Document Number: 001-92145 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 5, 2017
Automotive PSoC
®
4: PSoC 4000
Family Datasheet
Contents
Block Diagram .................................................................. 3
Functional Description ..................................................... 3
Functional Overview ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks .............................................................. 5
Fixed Function Digital .................................................. 5
GPIO ........................................................................... 5
Special Function Peripherals ....................................... 5
Pinouts .............................................................................. 6
Power ................................................................................. 8
Unregulated External Supply ....................................... 8
Regulated External Supply .......................................... 8
Development Support ...................................................... 9
Documentation ............................................................ 9
Online .......................................................................... 9
Tools ............................................................................ 9
Electrical Specifications ................................................ 10
Absolute Maximum Ratings ....................................... 10
Device Level Specifications ....................................... 11
Analog Peripherals .................................................... 14
Digital Peripherals ..................................................... 16
Memory ..................................................................... 18
System Resources .................................................... 18
Ordering Information ...................................................... 21
Part Numbering Conventions .................................... 21
Packaging ........................................................................ 23
Package Outline Drawings ........................................ 24
Acronyms ........................................................................ 26
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-92145 Rev. *F
Page 2 of 31
Automotive PSoC
®
4: PSoC 4000
Family Datasheet
Block Diagram
CPU Subsystem
PSoC 4000
32-bit
SWD/TC
SPCIF
Cortex
M0
16 MHz
MUL
NVIC, IRQMX
Flash
16 KB
Read Accelerator
SRAM
2 KB
SRAM Controller
ROM
4 KB
ROM Controller
AHB- Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
System Interconnect (Single/Multi Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
IOSS GPIO
(4x ports)
Power Modes
Active/ Sleep
Deep Sleep
High Speed I/O Matrix
20 x GPIOs
I/O Subsystem
Functional Description
PSoC 4000 devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000 family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers. It has the following advantages:
■
■
■
Robust flash protection
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
The debug circuits are enabled by default and can only be
disabled in firmware. If they are not enabled, the only way to
re-enable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000, with device security enabled, will have only limited
capability for failure analysis. This is a trade-off the PSoC 4000
allows the customer to make.
Allows disabling of debug features
Document Number: 001-92145 Rev. *F
2x LP Comparator
1x TCPWM
1x SCB-
I2C
CapSense
Page 3 of 31
Automotive PSoC
®
4: PSoC 4000
Family Datasheet
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4000 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
the CPU executes a subset of the Thumb-2 instruction set. This
enables fully compatible, binary, upward migration of the code to
higher performance processors, such as the Cortex-M3 and M4.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from the
Deep Sleep mode, allowing power to be switched off to the main
processor when the chip is in the Deep Sleep mode.
The CPU also includes a debug interface, the SWD interface,
which is a 2-wire form of JTAG. The debug configuration used for
PSoC 4000 has four breakpoint (address) comparators and two
watchpoint (data) comparators.
Flash
The PSoC 4000 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The low-power flash block is designed
to deliver zero wait-state (WS) access time at 16 MHz. The flash
accelerator delivers 85% of the single-cycle SRAM access
performance on average.
SRAM
Two KB of SRAM are provided with zero wait-state access at
16 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Clock System
The PSoC 4000 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that there are no metastable conditions.
The clock system for the PSoC 4000 consists of the internal main
oscillator (IMO) and the internal low-frequency oscillator (ILO)
and provision for an external clock.
Figure 1. PSoC 4000 MCU Clocking Architecture
IMO
Divide By
2,4,8
F
CPU
External Clock
(connects to GPIO pin P .4)
0
The F
CPU
signal can be divided down to generate synchronous
clocks for the analog and digital peripherals. There are four clock
dividers for the PSoC 4000, each with 16-bit divide capability The
16-bit capability allows flexible generation of fine-grained
frequency values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2% (24
and 32 MHz).
ILO Clock Source
The ILO is a very low power, 40-kHz oscillator, which is primarily
used to generate clocks for the watchdog timer (WDT) and
peripheral operation in Deep Sleep mode. ILO-driven counters
can be calibrated to the IMO to improve accuracy. Cypress
provides a software component, which does the calibration.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000 can be reset from a variety of sources including
a software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset on the 24-pin package. An internal POR is
provided on the 16-pin package. The XRES pin has an internal
pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4000 reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
System Resources
Power System
The power system is described in detail in the section on
Power
on page 8.
It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000 operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000 provides Active,
Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with instan-
taneous wake-up on a wake-up event. In Deep Sleep mode, the
high-speed clock and associated circuitry is switched off;
wake-up from this mode takes 35 µS.
Document Number: 001-92145 Rev. *F
Page 4 of 31
Automotive PSoC
®
4: PSoC 4000
Family Datasheet
The PSoC 4000 is not completely compliant with the I
2
C spec in
the following respect:
■
Analog Blocks
Low-power Comparators
The PSoC 4000 has a low-power comparator, which uses the
built-in voltage reference. Any one of up to 16 pins can be used
as a comparator input and the output of the comparator can be
brought out to a pin. The selected comparator input is connected
to the minus input of the comparator with the plus input always
connected to the 1.2-V voltage reference
Current DACs
The PSoC 4000 has two IDACs, which can drive any of up to 16
pins on the chip. These IDACs have programmable current
ranges.
Analog Multiplexed Buses
The PSoC 4000 has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on Ports 0, 1, and 2.
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I
2
C system.
GPIO
The PSoC 4000 has up to 20 GPIOs. The GPIO block imple-
ments the following:
■
Eight drive modes:
❐
Analog input mode (input and output buffers disabled)
❐
Input only
❐
Weak pull-up with strong pull-down
❐
Strong pull-up with weak pull-down
❐
Open drain with strong pull-down
❐
Open drain with strong pull-up
❐
Strong pull-up with strong pull-down
❐
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
Selectable slew rates for dV/dt related noise control to improve
EMI
■
■
■
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention.
Serial Communication Block (SCB)
The PSoC 4000 has a serial communication block, which imple-
ments a multi-master I
2
C interface.
I
2
C
Mode:
The hardware
block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4000 and effectively reduces I
2
C commu-
nication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I
2
C peripheral is compatible with the I
2
C Standard-mode and
Fast-mode devices as defined in the NXP I
2
C-bus specification
and user manual (UM10204). The I
2
C bus I/O is implemented
with GPIO in open-drain modes.
I
2
C
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (4 for PSoC 4000).
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4000 through a CSD block
that can be connected to up to 16 pins through an analog mux
bus via an analog switch (pins on Port 3 are not available for
CapSense purposes). CapSense function can thus be provided
on any available pin or group of pins in a system under software
control. A PSoC Creator component is provided for the
CapSense block to make it easy for the user.
Shield voltage can be driven on another mux bus to provide
water-tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
Document Number: 001-92145 Rev. *F
Page 5 of 31
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