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5962-9461106HXC

产品描述Cache SRAM Module, 512KX32, 45ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
产品类别存储    存储   
文件大小288KB,共40页
制造商White Microelectronics
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5962-9461106HXC概述

Cache SRAM Module, 512KX32, 45ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9461106HXC规格参数

参数名称属性值
厂商名称White Microelectronics
包装说明HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Reach Compliance Codeunknown
最长访问时间45 ns
其他特性ALSO CONFIGURABLE AS 2M X 8
备用内存宽度16
JESD-30 代码S-CPGA-P66
JESD-609代码e4
内存密度16777216 bit
内存集成电路类型CACHE SRAM MODULE
内存宽度32
功能数量1
端子数量66
字数524288 words
字数代码512000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织512KX32
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码PGA
封装形状SQUARE
封装形式GRID ARRAY
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度6.223 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式PIN/PEG
端子节距2.54 mm
端子位置PERPENDICULAR
Base Number Matches1

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REVISIONS
LTR
F
DESCRIPTION
Figure 1; changed case outline M to be available in either a single or
dual cavity package. Added vendor CAGE code 0EU86 for device
types 05 through 10. -sld
Added device types 11 through 16.
Add note to paragraph 1.2.2 and table I, conditions. Add thermal
resistance, junction-to-case (θ
JC
) for all case outlines. Add case
outline 9.
Table I, I
CC
change maximum limits and I
SB
change maximum limits.
Figure 1, case outline M, correct diagram adding "c" dimension, lead
thickness and change dimension A2 maximum from 0.020" to 0.025".
Figure 1, case outline 9, minimum dimension for D2/E2, change
0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm.
Table I; Operating supply current (I
CC
) changed the maximum limit for
device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for
device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld
Added device types 17 through 20. -sld
Added case outline A. -sld
Added case outline B. Added note to paragraph 1.2.4. -sld
Table I; Changed the I
OL
from 8 mA to 6 mA for device types 07-10
and 13 -20 for the V
OL
test. Editorial changes throughout. -sld
DATE (YR-MO-DA)
99-04-22
APPROVED
K. A. Cottongim
G
H
99-08-18
00-04-06
Raymond Monnin
Raymond Monnin
J
00-06-19
Raymond Monnin
K
L
01-5-16
01-12-21
Raymond Monnin
Raymond Monnin
M
N
P
R
02-11-18
03-02-24
03-12-19
04-05-03
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
R
15
R
16
R
17
R
18
REV
SHEET
PREPARED BY
Gary Zahn
CHECKED BY
Michael C. Jones
R
19
R
20
R
21
R
1
R
22
R
2
R
23
R
3
R
24
R
4
R
25
R
5
R
26
R
6
R
27
R
7
R
28
R
8
R
29
R
9
R
30
R
10
R
31
R
11
R
12
R
13
R
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 512K x 32-BIT, STATIC RANDOM
ACCESS MEMORY, CMOS
SIZE
A
SHEET
CAGE CODE
DRAWING APPROVAL DATE
95-11-13
REVISION LEVEL
R
67268
1 OF
31
5962-94611
5962-E251-04
DSCC FORM 2233
APR 97
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