TSM7900D
20V Dual N-Channel MOSFET w/ESD Protected
TDFN 3x3
Pin Definition:
1. Source 1
2. Gate 1
3. Source 2
4. Gate 2
5, 6, 7, 8. Drain
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
(mΩ)
20
32 @ V
GS
= 4.5V
40 @ V
GS
= 2.5V
I
D
(A)
6.5
5.0
Features
●
●
●
Advance Trench Process Technology
High Density Cell Design for Ultra Low On-resistance
ESD Protect 2KV
Block Diagram
Application
●
●
Specially Designed for Li-on Battery Packs
Battery Switch Application
Ordering Information
Part No.
TSM7900DCQ RF
Package
TDFN 3x3
Packing
3Kpcs / 7” Reel
Dual N-Channel MOSFET
Absolute Maximum Rating
(Ta = 25
o
C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current, V
GS
@4.5V.
Pulsed Drain Current, V
GS
@4.5V
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
Operating Junction Temperature
Operating Junction and Storage Temperature Range
a,b
o
o
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
T
J
, T
STG
Ta = 25 C
Ta = 75 C
Limit
20
±12
6
30
1.4
Unit
V
V
A
A
A
W
o
o
1.25
0.8
+150
-55 to +150
C
C
Thermal Performance
Parameter
Junction to Foot (Drain) Thermal Resistance
Junction to Ambient Thermal Resistance (PCB mounted)
Notes:
a. Pulse width limited by the Maximum junction temperature
b. Surface Mounted on FR4 Board, t
≤
5 sec.
Symbol
RӨ
JF
RӨ
JA
Limit
30
50
Unit
o
o
C/W
C/W
1/6
Version: B07
TSM7900D
20V Dual N-Channel MOSFET w/ESD Protected
Electrical Specifications
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
b
Conditions
V
GS
= 0V, I
D
= 250uA
V
DS
= V
GS
, I
D
= 250uA
V
GS
= ±12V, V
DS
= 0V
V
DS
= 16V, V
GS
= 0V
V
DS
= 5V, V
GS
= 4.5V
V
GS
= 4.5V, I
D
= 6.0A
V
GS
= 2.5V, I
D
= 5.0A
V
DS
= 10V, I
D
= 6.0A
I
S
= 1.5A, V
GS
= 0V
Symbol
BV
DSS
V
GS(TH)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
g
fs
V
SD
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
Min
20
0.6
--
--
30
--
--
--
--
--
--
--
--
--
--
Typ
--
0.8
--
--
--
30
35
30
0.6
15
3.4
1.2
950
450
125
140
210
3700
2000
Max
--
1.0
±100
1.0
--
35
40
--
1.2
20
--
--
--
--
--
200
250
4800
2600
Unit
V
V
nA
uA
A
mΩ
S
V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching
c
V
DS
= 10V, I
D
= 6A,
V
GS
= 4.5V
V
DS
= 10V, V
GS
= 0V,
f = 1.0MHz
nC
pF
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
V
DD
= 10V, R
L
= 10Ω,
I
D
= 1A, V
GEN
= 4.5V,
--
--
--
--
nS
R
G
= 6Ω
Turn-Off Fall Time
t
f
Notes:
a. pulse test: PW 300µS, duty cycle 2%
b. For DESIGN AID ONLY, not subject to production testing.
b. Switching time is essentially independent of operating temperature.
2/6
Version: B07
TSM7900D
20V Dual N-Channel MOSFET w/ESD Protected
Electrical Characteristics Curve
(Ta = 25
o
C, unless otherwise noted)
Output Characteristics
Transfer Characteristics
On-Resistance vs. Drain Current
Gate Charge
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
3/6
Version: B07
TSM7900D
20V Dual N-Channel MOSFET w/ESD Protected
Electrical Characteristics Curve
(Ta = 25
o
C, unless otherwise noted)
On-Resistance vs. Gate-Source Voltage
Threshold Voltage
Single Pulse Power
Normalized Thermal Transient Impedance, Junction-to-Ambient
4/6
Version: B07
TSM7900D
20V Dual N-Channel MOSFET w/ESD Protected
TDFN Mechanical Drawing
TDFN 3x3 DIMENSION
DIM
A
B
C
D
E
F
G
H
I
J
MILLIMETERS
MIN.
1.750
0.470
0.270
2.950
2.950
2.250
0.177
0.610
0.005
0.650
TYP.
1.800
0.520
0.320
3.000
3.000
2.300
0.203
0.660
0.020
0.750
MAX.
1.850
0.570
0.370
3.050
3.050
2.350
0.280
0.710
0.050
0.850
5/6
Version: B07
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