Data Sheet AS1105
Serially Interfaced, 4-Digit LED Driver
AS1105
Key Features
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DATA SHEET
Cost effective version of AS1100 functionality for
applications up to 4-Digits
10MHz Serial Interface
Individual LED Segment Control
Decode/No-Decode Digit Selection
20µA Low-Power Shutdown (Data Retained)
Extremely low Operating Current 0.5mA in open loop
Digital and Analog Brightness Control
Display Blanked on Power-Up
Drive Common-Cathode LED Display
Software Reset
1
Optional External clock
20 pin SO Packages
Every individual segment can be addressed and updated
separately. Only one external resistor is required to set the
current through the LED display. Brightness can be
controlled either in an analog or digital way. The user can
choose the internal code-B decoder to display numeric
digits or to address each segment directly. The AS1105
features an extremely low shutdown current of only 20µA.
and an operational current of less than 500µA. The number
of visible digits can be programmed as well. The AS1105
can be reset by software and an external clock can be used.
Several test modes support easy debugging.
AS1105 is offered in a 20 SOIC package.
Applications
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General Description
The AS1105 is an LED driver for 7 segment numeric
displays of up to 4 digits. The AS1105 can be programmed
via a conventional 4 wire serial interface. It includes a BCD
code-B decoder, a multiplex scan circuitry, segment and
display drivers and a 32 Bit memory. The memory is used to
store the LED settings, so that continuous reprogramming is
not necessary.
Bar-Graph Displays
Industrial Controllers
Panel Meters
LED Matrix Displays
White Goods
TOP
DOUT 1
DIN
2
20 SEG D
19 SEG DP
18 SEG E
17 SEG C
16 VDD
15 ISET
+5V
9.53k
ISET
MOSI
µP I/O
SCK
DIN
LOAD
CLK
SEG A-G
SEP DP
VDD
DIG0-DIG3
4 Digits
DIG0 3
GND
4
DIG2 5
DIG3 6
GND
7
AS1105
14 SEG G
13
12
11
SEG B
SEG F
SEG A
DIG1 8
LOAD
9
CLK 10
GND GND
Typical Application Circuit
8 Segments
SO
Pin Configuration
4-Digit µP Display
1
Software Reset and external clock are not supported by
MAX7219
Revision 1.32, Oct. 2004
Page 1 of 12
Data Sheet AS1105
Absolute Maximum Ratings
Voltage (with respect to GND)
VDD
DIN, CLK, LOAD
All Other Pins
Current
DIG0–DIG3 Sink Current
SEGA–G, DP Source Current
Continuous Power Dissipation (TA = +85°C)
Wide SO (derate 11.8mW/°C above +70°C)
Operating Temperature Ranges (T
MIN
to T
MA X
)
AS1105xL
AS1105xE
Storage Temperature Range
Package body temperature
2
-0.3V to 6V
-0.3V to 6V
-0.3V to (VDD +0.3V)
500mA
100mA
941mW
0°C to +70°C
-40°C to +85°C
-65°C to +150°C
+240°C
Electrical Characteristics
(VDD = 5V, R
SET
= 9.53kΩ±1%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
Operating Supply Voltage
Symbol Conditions
VDD
All digital inputs at VDD or GND, T
A
=
Shutdown Supply Current
IDD
SD
+25°C
R
SET
= open circuit
Operating Supply Current
IDD All segments and decimal point on, I
SEG
= -
40mA
Display Scan Rate
f
OSC
Digit Drive Sink Current
I
DIGIT
V
OUT
= 0.65V
Segment Drive Source Current
I
SEG
T
A
= +25°C, V
OUT
= (VDD -1V)
Segment Drive Current
∆I
SEG
Matching
Digit Drive Source Current
I
DIGIT
Digit off, V
DIG IT
= (VDD -0.3V)
Segment Drive Sink Current
I
SEG
Segment off, V
SEG
= 0.3V
Logic Inputs
Input Current DIN, CLK, LOAD I
IH
, I
IL
V
IN
= 0V or VDD
Logic High Input Voltage
V
IH
Min
4.0
Typ
5.0
20
Max
5.5
50
500
330
500
320
-30
800
-40
3.0
-2
5
-1
3.5
1
1300
-45
Units
V
µA
µA
mA
Hz
mA
mA
%
mA
mA
µA
V
2
The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020B “Moisture/Reflow Sensitivity
Classification for non-hermetic Solid State Surface Mount Devices”.
Revision 1.32, Oct. 2004
Page 2 of 12
Data Sheet AS1105
Parameter
Logic Low Input Voltage
Output High Voltage
Output Low Voltage
Hysteresis Voltage
Timing Characteristics
CLK Clock Period
CLK Pulse Width High
CLK Pulse Width Low
CLK Rise to LOAD Rise Hold
Time
DIN Setup Time
DIN Hold Time
Output Data Propagation Delay
LOAD Rising Edge to Next
Clock Rising Edge
Minimum LOAD Pulse High
Data-to-Segment Delay
Symbol
V
IL
V
OH
V
OL
V
I
t
CP
t
CH
t
CL
t
CSH
t
DS
t
DH
t
DO
t
LDCK
t
CSW
t
DSPD
Conditions
DOUT, I
SOURCE
= -1mA
DOUT, I
SINK
= 1.6mA
DIN, CLK, LOAD
Min
VDD - 1
Typ
Max
0.8
0.4
1
100
50
50
0
25
0
Units
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
C
LOAD
= 50pF
50
50
25
2.25
Pin Description
Pin
1
2
3,8,5,6
4, 7
9
Name
DOUT
DIN
DIG0–DIG3
GND
LOAD
Function
Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The
output is never set to high impedance.
Data input. Data is programmed into the 16Bit shift register on the rising CLK edge
4 digit driver lines that sink the current from the common cathode of the display.
In shutdown mode the AS1105 switches the outputs to VDD
both GND pins must be connected
Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into
the register.
Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial
data is clocked into the internal shift register with the rising edge of the CLK signal. On the
DOUT pin the data is applied with the falling edge of CLK.
Seven segment driver lines including the decimal point. When a segment is turned off the
output is connected to GND.
The current into I
SET
determines the peak current through the segments and therefore the
brightness.
Positive Supply Voltage (+5V)
10
11–14, 17–20
15
16
CLK
SEG A–G,
DP
ISET
VDD
Revision 1.32, Oct. 2004
Page 3 of 12
Data Sheet AS1105
LOAD
t
CSW
t
CS
t
CL
t
CH
t
CP
t
LDCK
CLK
t
DH
t
DS
DIN
D15
D14
D1
D0
t
DO
DOUT
Figure 1: Timing diagram
D15 D14 D13 D12 D11 D10 D9
X
X
X
X
Address
Table 1: Serial data format (16 bits)
D8
D7 D6
MSB
D5
D4 D3
Data
D2
D1
D0
LSB
Detailed Description
Serial-Addressing Modes
Programming of the AS1105 is done via the 4 wire serial
interface. A programming sequence consists of 16-bit
packages. The data is shifted into the internal 16 Bit
register with the rising edge of the CLK signal. With the
rising edge of the LOAD signal the data is latched into a
digital or control register depending on the address. The
LOAD signal must go to high after the 16
th
rising clock
edge. The LOAD signal can also come later but just before
the next rising edge of CLK, otherwise data would be lost.
The content of the internal shift register is applied 16.5
clock cycles later to the DOUT pin. The data is clocked out
at the falling edge of CLK. The Bits of the 16Bit-
programming package are described in table 1. The first 4
Bits D15-D12 are ”don’t care, D11-D8 contain the address
and D7-D0 contain the data. The first bit is D15, the most
significant bit (MSB). The exact timing is given in figure 1.
Digit and Control Registers
The AS1105 incorporates 12 registers, which are listed in
Table 2. The digit and control registers are selected via the
4Bit address word. The 4 digit registers are realized with a
32bit memory. Each digit can be controlled directly without
rewriting the whole contents. The control registers consist
of decode mode, display intensity, number of scanned
digits, shutdown, display test and reset/external clock
register.
Shutdown Mode
The AS1105 features a shutdown mode, where it consumes
only 20µA current. The shutdown mode is entered via a
write to register 0Ch. Then all segment current sources are
pulled to ground and all digit drivers are connected to VDD,
so that nothing is displayed. All internal digit registers keep
the programmed values. The shutdown mode can either be
used for power saving or for generating a flashing display
by repeatedly entering and leaving the shutdown mode. The
AS1105 needs typically 250µs to exit the shutdown mode.
During shutdown the AS1105 is fully programmable. Only
the display test function overrides the shutdown mode.
Initial Power-Up
After powering up the system all register are reset, so that
the display is blank. The AS1105 starts the shutdown mode.
All registers should be programmed for normal operation.
The default settings enable only scan of one digit, the
internal decoder is disabled, data register and intensity
register are set to the minimum value.
Revision 1.32, Oct. 2004
Page 4 of 12
Data Sheet AS1105
Decode-Mode Register
In the AS1105 a BCD decoder is included. Every digit can
be selected via register 09h to be decoded. The BCD code
consists of the numbers 0-9, E,H, L,P and -. In register 09h
a logic high enables the decoder for the appropriate digit. In
case that the decoder is bypassed (logic low) the data Bits
D7-D0 correspond to the segment lines of the AS1105. In
table 4 some possible settings for register 09h are shown.
Bit D7, which corresponds to the decimal point, is not
affected by the settings of the decoder. Logic high means
that the decimal point is displayed. In table 5 the font of the
Code B decoder is shown. In table 6 the correspondence of
the register to the appropriate segments of a 7 segment
display is shown (see figure 2)
Intensity Control and Interdigit Blanking
Brightness of the display can be controlled in an analog way
by changing the external resistor (R
SET
). The current, which
flows between VDD and I
SET
, defines the current that flows
through the LEDs. The LED current is 100 times the I
SET
current. The minimum value of R
SET
should be 9.53kΩ,
which corresponds to 40mA segment current. The
brightness of the display can also be controlled digitally via
register 0Ah. The brightness can be programmed in 16
steps and is shown in table 7. An internal pulse width
modulator controls the intensity of the display.
Scan-Limit Register
The scan limit register 0Bh selects the number of digits
displayed. When all 4 digits are displayed the update
frequency is typically 800Hz. If the number of digits
displayed is reduced, the update frequency is reduced as
well. The frequency can be calculated using 8fOSC/N,
where N is the number of digits. Since the number of
displayed digits influences the brightness, the resistor R
SET
Register Data
D5 D4 D3 D2
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
1
should be adjusted accordingly. Table 9 shows the
maximum allowed current, when fewer than 4 digits are
used. To avoid differences in brightness the scan limit
register should not be used to blank portions of the display
(leading zeros).
Address
D15–D12 D11 D10
X
0
0
X
0
0
X
0
0
X
0
0
X
0
1
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
0
1
1
1
1
Hex
Code
0xX0
0xX1
0xX2
0xX3
0xX4
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
Register
No-Op
Digit 0
Digit 1
Digit 2
Digit 3
Decode
Mode
Intensity
Scan Limit
Shutdown
Not used
Reset and
ext. Clock
Display
Test
D9
0
0
1
1
0
0
1
1
0
0
1
1
D8
0
1
0
1
0
1
0
1
0
1
0
1
Table 2: Register address map
Mode
Shutdown
Mode
Normal
Operation
Address Code
Register Data
D7 D6 D5 D4 D3 D2 D1 D0
(Hex)
0xXC
0xXC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Table 3: Shutdown register format (address (hex) = 0xXC)
Decode Mode
No decode for digits 4–0
Code B decode for digit 0
No decode for digits 4–1
Code B decode for digits
3–0
Code B decode for digits
4–0
D7
0
0
0
1
D6
0
0
0
1
D1
0
0
1
1
D0
0
1
1
1
Hex Code
0x00
0x01
0x0F
0xFF
Table 4: Decode-mode register examples (address (hex) = 0xX9)
Revision 1.32, Oct. 2004
Page 5 of 12
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