SMDA05C THRU SMDA24C
PROTECTION PRODUCTS
Description
The SMDAxxC series of TVS arrays are designed to
provide bidirectional protection for sensitive electronics
from damage or latch-up due to ESD, lightning and
other voltage-induced transient events. Each device
will protect four data or I/O lines. They are available
with operating voltages of 5V, 12V, 15V and 24V.
TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable charac-
teristics for board level protection including fast re-
sponse time, low operating and clamping voltage and
no device degradation. The low profile SO-8 package
allows the user to protect up to four independent lines
with one package. The SMDAxxC series is suitable
protection for sensitive semiconductors components
such as microprocessors, ASICs, transceivers, trans-
ducers, and CMOS memory.
The SMDAxxC series devices may be used to meet the
ESD immunity requirements of IEC 61000-4-2, level 4
for air and contact discharge.
Bidirectional TVS Array
for Protection of Four Lines
Features
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20µs)
Bidirectional protection
Small SO-8 package
Protects four I/O lines
Working voltages: 5V, 12V, 15V and 24V
Low leakage current
Low operating and clamping voltages
Solid-state silicon avalanche technology
Mechanical Characteristics
JEDEC SO-8 package
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tube or Tape and Reel per EIA 481
Applications
Data and I/O Lines
Microprocessor based equipment
Notebooks, Desktops, and Servers
Instrumentation
LAN/WAN equipment
Peripherals
Serial and Parallel Ports
Schematic & PIN Configuration
1
8
2
7
3
6
4
5
SO-8 (Top View)
Revision 08/15/06
1
www.semtech.com
SMDA05C THRU SMDA24C
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20µs)
ESD Voltage (HBM per IEC 61000-4-2)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
pk
V
ESD
T
L
T
J
T
STG
Value
300
>25
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
kV
°C
°C
°C
Electrical Characteristics (T=25
o
C)
SMDA05C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Maximum Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
tp = 8/20µs
V
R
= 0V, f = 1MHz
6
20
9.8
11
17
350
Conditions
Minimum
Typical
Maximum
5
Units
V
V
µA
V
V
A
pF
SMDA12C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Maximum Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
tp = 8/20µs
V
R
= 0V, f = 1MHz
13.3
1
19
24
12
120
Conditions
Minimum
Typical
Maximum
12
Units
V
V
µA
V
V
A
pF
2005 Semtech Corp.
2
www.semtech.com
SMDA05C THRU SMDA24C
PROTECTION PRODUCTS
Electrical Characteristics
(Continued)
SMDA15C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Maximum Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 15V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
tp = 8/20µs
V
R
= 0V, f = 1MHz
16.7
1
24
30
10
75
Conditions
Minimum
Typical
Maximum
15
Units
V
V
µA
V
V
A
pF
SMDA24C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Maximum Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 24V, T=25°C
I
PP
= 1A, tp = 8/20µs
I
PP
= 5A, tp = 8/20µs
tp = 8/20µs
V
R
= 0V, f = 1MHz
26.7
1
43
55
5
50
Conditions
Minimum
Typical
Maximum
24
Units
V
V
µA
V
V
A
pF
2005 Semtech Corp.
3
www.semtech.com
SMDA05C THRU SMDA24C
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
PP
(kW)
110
100
90
% of Rated Power or I
PP
1
80
70
60
50
40
30
20
10
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
0
25
50
75
100
o
Power Derating Curve
0.1
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
PP
Waveform
Parameters:
tr = 8µs
td = 20µs
e
-t
Percent of I
ESD Pulse Waveform (IEC 61000-4-2)
Level
IEC 61000-4-2 Discharge Parameters
First
Peak
Current
(A )
1
2
3
4
7.5
15
22.5
30
Peak
Current
at 30 ns
(A )
4
8
12
16
Peak
Current
at 60 ns
(A )
8
4
6
8
Test
Test
Voltage
Voltage
(Contact
(A ir
Discharge) Discharge)
(kV)
( kV )
2
4
6
8
2
4
8
15
2005 Semtech Corp.
4
www.semtech.com
SMDA05C THRU SMDA24C
PROTECTION PRODUCTS
Applications Information
Device Connection for Protection of Four Data Lines
The SMDAxxC series of devices are designed to protect
up to four data lines. The devices are connected as
follows:
The SMDAxxC are bidirectional devices and are
designed for use on lines where the normal operat-
ing voltage is above and below ground. Pins 1, 2,
3, and 4 are connected to the protected lines.
Pins 5, 6, 7, and 8 are connected to ground. Since
the device is electrically symmetrical, these connec-
tions may be reversed. The ground connections
should be made directly to the ground plane for
best results. The path length is kept as short as
possible to reduce the effects of parasitic induc-
tance in the board traces.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
2005 Semtech Corp.
5
Circuit Diagram
1
8
2
7
3
6
4
5
I/O Line Protection
Typical Connection
To Protected
Device
1
8
2
7
Ground
3
6
4
5
From Connector
www.semtech.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
