Video Accessory IC Series
For portable image equipment
Upscaler IC
BU1521GVW
●
Description
BU1521GVW upscales and interpolates images when upconverting to the HDTV (Maximum 1080P) format from the usual SDTV
(NTSC/PAL) format.
High quality IP change・up scale management is realized by the frame memory less operate.
It is the LSI which is the most suitable for the compact system of the mobile.
●
Features
1）Input format
480i or 576i(ITUR BT656) YCbCr 4:2:2(ITUR BT601) 8bit Digital Interface
2）Output Format
480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit Digital Interface
480p or 576p(SMPTE 293・ITUR BT1358) YCbCr 4:2:2 16bit Digital Interface
1080/59.94i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/50i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/59.94p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
1080/50p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface
3）IP conversion function
Conversion function from interlace to progressive
4）Upscale function
Horizontal direction: 720 pixels pass-through or upscaling to 1920 pixels
Vertical direction: up scaling to 480, 576, 540, and 1080 pixels
5）Filter function
5 × 5 filtering function over input data
Filter coefficient is programmable with registers
6）Register access
Register read/write through the SPI interface
Burst write/read support
7）Built-in PLL
Input frequency 27MHz
Output frequency 74.25MHz,74.175824MHz,148.5MHz,148.351648MHz
8）Power-down mode and through-mode support
Power-down mode can be controlled through STBY pin or register setting.
Through-mode can be selected by register setting.
9）Supply voltage
VDD(core voltage )1.15V½1.25V、AVDD(PLL)=2.7V~3.3V、
VDDIO1(SDTV input)=1.7V½3.6V、VDDIO2(control)=2.7V½3.3V、
VDDIO3(HDTV output)=1.7V½1.9V
10）Package
63 pin, BGA package (SBGA063W060, Size = 6 mm × 6 mm, 0.65 mm pitch)
Aplications
Digital Video Camera、Digital still camera , Video game, a portable DVD
No.09069EAT02
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© 2009 ROHM Co., Ltd. All rights reserved.
1/15
2009.05 - Rev.A
BU1521GVW
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Absolute Maximum Rating
Parameter
Supply voltage 1 (SD input)
Supply voltage 2 (Control)
Supply voltage 3 (HD output)
Supply voltage 4 (PLL)
Supply voltage 5 (CORE)
Input voltage 1
Input voltage 2
Input voltage 3
Storage temperature range
Power dissipation
Table. 1 Absolute maximum rating
Symbol
Rating
VDDIO1
-0.3½+4.2
VDDIO2
-0.3½+4.2
VDDIO3
-0.3½+4.2
AVDD
-0.3½+4.2
VDD
-0.3½+1.68
VIN1
-0.3½VDDIO1+0.3
VIN2
-0.3½VDDIO2+0.3
VIN3
-0.3½VDDIO3+0.3
Tstg
-25½+125
PD
330*1, 1200*2
Technical Note
Unit
V
V
V
V
V
V
V
V
ºC
mW
he rating 1C.
*1 IC only. In the case exceeding 25°C, 3.3 mW should be reduced at the rating 1C.
*2 When packaging a glass epoxy board of 114.3 × 76.2 × 1.6 mm. In the case exceeding 25°C, 12 mW should be reduced at t
* Has not been designed to withstand radiation.
* Operation is not guaranteed.
●
Operating Conditions
Parameter
Supply voltage 1 (SD input)
Supply voltage 2 (Control)
Supply voltage 3 (HD output)
Supply voltage 4 (PLL)
Supply voltage 5 (CORE)
Operating temperature range
Table. 2 Operating conditions
Symbol
Min
Typ
VDDIO1
1.7
3.3
VDDIO2
2.7
3.0
VDDIO3
1.7
1.8
AVDD
2.7
3.0
VDD
1.15
1.2
Topr
-25
-
Max
3.6
3.3
1.9
3.3
1.25
85
Unit
V
V
V
V
V
℃
●
Electrical Characteristics (DC Characteristics)
Table. 3 Electric characteristics
Parameter
Operational current (CORE)
Operational current (IO)
Operational current (CORE)
Operational current (IO)
Static current
Input “H” current
Input “L” current
Input “H” voltage 1
Input “L” voltage 1
Input “H” voltage 2
Input “L” voltage 2
Hysteresis voltage range 2
Output “H” voltage 1
Output “L” voltage 1
Output “H” voltage 2
Output “L” voltage 2
Symbol
IDD1
IDD2
IDD3
IDD4
IDDst
IIH
IIL
VIH1
VIL1
VIH2
VIL2
Vhys2
VOH1
VOL1
VOH2
VOL2
Specification
MIN
TYP
MAX
-
150
200
-
-
-
-
-10
-10
VDDIO1
*0.8
-0.3
VDDIO1
*0.85
-0.3
-
VDDIO2
-0.4
0.0
VDDIO3
-0.2
0.0
40
15
10
-
-
-
-
-
-
-
0.75
-
-
-
-
80
20
20
800
10
10
VDDIO1
+0.3
VDDIO1
*0.2
VDDIO1
+0.3
VDDIO1
*0.15
-
VDDIO2
0.4
VDDIO3
0.2
Unit
mA
mA
mA
mA
μA
μA
μA
V
V
V
V
V
V
V
V
V
Conditions
When operated with HDCLK = 148.5 MHz
When operated with HDCLK = 148.5 MHz and
external capacitor of 5pF
When operated with DCLK = 27 MHz
When operated with HDCLK = 27 MHz and
external capacitor of 5pF
In standby mode
VIH=VDDIO1/2
VIL=GND
Ordinary input (Including input mode of I/O pin)
Ordinary input (Including input mode of I/O pin)
Hysteresis input
Hysteresis input
Hysteresis input
IOH1=-1.0mA(DC)
IOL1=1.0mA(DC)
IOH1=-1.0mA(DC)
IOL1=1.0mA(DC)
SDOUT
SDOUT
HD output pin
HD output pin
(When not otherwise specified, under the conditions of VDD = 1.20 V, VDDIO1 = 3.3 V, VDDIO3 = 1.8 V, VDDIO2 = AVDD = 3.0 V, AVSS = GND = 0.0 V, and Ta = 25C)
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2/15
2009.05 - Rev.A
BU1521GVW
Technical Note
●
1.
Electrical Characteristics (AC Characteristics)
3-wire serial interface timing
SCSB
t
word
t
Wt
SCLK
0
1
5
6
7
0
1
5
6
7
t
wcs
SCSB
t
css
SCLK
t
wsclk
t
csh
t
sds
SDIN
t
sdh
t
sdo
SDOUT
t
sdo
Fig. 1 3-wire serial interface format
Symbol
t
wsclk
t
wcs
t
css
t
sds
t
csh
t
sdh
t
sdo
t
word
t
wt
Table. 4 3-wire serial interface format
Description
MIN
SCLK clock cycle
200
SCSB access interval
1
SCSB setup time
200
SDIN setup time
30
SCSB holding time
1
SDIN holding time
30
Time from trailing of the clock to the establishment of SDOUT
-
1 word write time
2.5
1 word write interval
1
TYP
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
60
-
-
Unit
ns
μs
ns
ns
μs
ns
ns
μs
μs
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© 2009 ROHM Co., Ltd. All rights reserved.
3/15
2009.05 - Rev.A
BU1521GVW
Technical Note
2.
Image Data Input Timing
½CIP
½CIL
½CIH
CLKIN
DI0-15
½DIS ½DIH
Fig. 2 Image Data Input Timing
Table. 5 Image Data Input Timing
Symbol
t
CIP
d
CKI
t
DIS
t
DIH
3.
CLKIN Clock cycle
CLKIN clock duty (tCIL/tCIP or tCIH/tCIP)
Data setup time from the CLKIN rise
Data holding time from the CLKIN rise
Description
MIN
-
45
2
3
TYP
37.03
50
-
-
MAX
-
55
-
-
Unit
ns
%
ns
ns
Image Data Output Timing
½COP
½COL
½COH
CLKOUT
DO0-15
½DOD
Fig. 3 Image Data Output Timing
Table. 6 Image Data Output Timing
Symbol
t
COP
d
CKO
t
DOD
t
DOD
t
JIT
CLKOUT Clock cycle
CLKOUT clock duty (tCOL/tCOP or tCOH/tCOP) *
Time from the rise of CLKOUT to the establishment of DO0-15
(Wh from the rise of CLKOUT to the establishment of DO0-15
)
Time 27MH i
(Wh PLL i
d)
Output jitter of CLKOUT (1 us cycle)
Description
MIN
6.734
45
1
1
-
TYP
-
-
-
-
-
MAX
-
55
12
5.734
2
Unit
ns
%
ns
ns
ns
* When PLL is used. When 27 MHz is output, the input clock duty is 50%.
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© 2009 ROHM Co., Ltd. All rights reserved.
4/15
2009.05 - Rev.A
BU1521GVW
Technical Note
●
Pin configuration diagram (Bottom View)
Fig. 4 Pin configuration diagram of BU1521GVW (Bottom view).
H
16
GND
19
DI15
21
DI1
24
SCSB
25
SDIN
28
STBY
30
DO1
32
GND
G
14
DI13
17
DI11
20
DI2
23
SCLK
26
SDOUT
29
CLKOUT
33
DO0
35
DO2
F
12
DI10
13
DI7
15
GND
22
RESETB
27
VDDIO2
31
VDD
36
DO4
37
DO3
E
9
DI14
10
DI0
11
GND
18
VDD
34
VDDIO3
38
GND
39
DO6
40
DO5
D
8
DI9
7
DI12
6
VDDIO1
2
AVDD
50
GND
43
VDD
42
DO8
41
DO7
C
4
DI5
63
GND
59
AVSS
54
VDDIO3
47
GND
45
DO10
44
DO9
B
3
DI6
1
DI3
61
DI8
58
GND
55
TEST0
52
DO14
49
DO12
46
DO11
A
64
GND
62
DI4
60
CLKIN
57
TEST2
56
TEST1
53
DO15
51
DO13
48
GND
1
2
3
4
5
6
7
8
Fig. 4 BU1521GVW Pin configuration diagram(Bottom View)
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© 2009 ROHM Co., Ltd. All rights reserved.
5/15
2009.05 - Rev.A
stm32/stm8
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