19-0524; Rev 1; 8/06
Multiple-Output Clock Generators with
Dual PLLs and OTP
MAX9471/MAX9472
General Description
The MAX9471/MAX9472 multipurpose clock generators
are ideal for consumer and communication applica-
tions. The MAX9471/MAX9472 feature two buffered
phase-locked loop (PLL) outputs that can be indepen-
dently set from 4MHz to 200MHz. These devices also
provide one (MAX9472) or two (MAX9471) buffered
outputs of the reference clock.
The MAX9471 outputs a set of MPEG/AC3 audio and
video frequencies most commonly used in consumer
applications. The MAX9472 outputs a set of common
audio frequencies. These frequencies are selected
through an I
2
C
†
interface (MAX9471) or by setting the
three-level FS pins. The MAX9471/MAX9472 feature a
one-time-programmable (OTP) ROM, allowing one-time
programming of the two PLL outputs.
The MAX9471/MAX9472 include two basic configura-
tions. In one configuration, the OTP ROM sets PLL1 out-
put to any frequency between 4MHz to 200MHz, and
the I
2
C interface (MAX9471) or programmable pins set
the PLL2 output frequency to a set of audio and video
frequencies. In the other configuration, the OTP ROM
sets both PLL1 and PLL2 frequencies to fixed values
between 4MHz to 200MHz. In both cases, the reference
output is available, but the OTP ROM can disable it.
The OTP ROM on the MAX9471/MAX9472 is factory set
based on the customer requirements. Contact the factory
for samples with preferred frequencies.
The devices operate from a 3.3V supply and are specified
over the -40°C to +85°C extended temperature range.
The MAX9471 is available in a 20-pin TQFN package. The
MAX9472 is available in a 14-pin TSSOP package.
Features
♦
5MHz to 50MHz Input Clock Reference
♦
Crystal or Input-Clock-Based Reference
♦
Two Fractional-N Feedback PLLs (4MHz to
200MHz) with Buffered Outputs
♦
Two Buffered Outputs of Reference Clock
♦
OTP for Factory-Preset PLL Frequencies
Available (Contact Factory)
♦
Programmable Through I
2
C Interface or Three-
Level Logic Pins for Video or Audio Clocks
♦
Low-RMS Jitter PLL (14ps for 45MHz)
♦
Integrated VCXO with ±200ppm Tuning Range
♦
Available in 20-Pin TQFN and 14-Pin TSSOP
Packages
♦
+3.3V Supply
♦
-40°C to +85°C Temperature Range
Ordering Information
PART
MAX9471ETP+**
MAX9472
EUD+**
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
14 TSSOP
PKG
CODE
U14-2
20 TQFN-EP* T2055-5
*EP
= Exposed pad.
**Marking
is for samples only. Contact factory for ordering information.
+Denotes
lead-free package.
Pin Configurations
Digital TVs
Communication Systems
Data Networking Systems
Set-Top Boxes
Home Entertainment Centers
Multimedia PCs
V
DD
X2
X1
FSO/SCL
FS1/SDA
16
17
18
19
20
1
2
3
4
5
TOP VIEW
15
14
13
12
11
10
9
GND
V
DD
V
DD
FS2
Applications
PD
GND
I.C.
CLK4
CLK3
CLK2
MAX9471
8
7
6
+
†P,
Is
a-
ps
ts.
TUNE
V
DDA
TQFN (5mm x 5mm)
Pin Configurations continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
AGND
CLK1
GND
Multiple-Output Clock Generators with
Dual PLLs and OTP
MAX9471/MAX9472
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ...........................................................-0.3V to +4.0V
V
DDA
to AGND ......................................................-0.3V to +4.0V
AGND to GND ......................................................-0.3V to +0.3V
All Other Pins to GND ..................................-0.3V to V
DD
+ 0.3V
Short-Circuit Duration
(all LVCMOS outputs)..............................................Continuous
ESD Protection (Human Body Model)..................................±2kV
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TQFN (derate 21.3mW/°C above +70°C) .......2758mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......796.8mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DDA
= +3.0V to +3.6V and T
A
= -40°C to +85°C. Typical values at V
DD
= V
DDA
= 3.3V, T
A
= +25°C, unless otherwise noted.)
(Note 1)
PARAMETER
Input High Level
Input Low Level
Input Current High Level
Input Current Low Level
Input High Level
Input Low Level
Input Open Level
Input Current
SYMBOL
V
IH1
V
IL1
I
IH1
I
IL1
V
IH2
V
IL2
V
IO2
I
IL2,
I
IH2
V
IL2
= 0 or V
IH2
= V
DD
1.27
-10
0.7 x
V
DD
0.3 x
V
DD
-1
I
SINK
= 4mA
(Note 3)
V
DD
-
0.6
0.4
3.0
3.0
CLK1 at 125MHz and CLK2 at 74.1758MHz;
all outputs not loaded
PD
= low
12
60
3.6
3.6
8.4
+1
0.4
V
IN
= V
DD
V
IN
= 0
-20
2.5
0.8
2.10
+10
CONDITIONS
MIN
2.0
0
TYP
MAX
V
DD
0.8
20
UNITS
V
V
µA
µA
V
V
V
µA
LVCMOS INPUTS (PD, X1 as a reference INPUT CLK)
THREE-LEVEL INPUTS (FS0, FS1, FS2, as FS2 = open)
SERIAL INTERFACE (SCL, SDA) (Note 2) (MAX9471)
Input High Level
Input Low Level
Input-Leakage Current
Low-Level Output
Input Capacitance
CLOCK OUTPUTS (CLK_)
Output High Level
Output Low Level
POWER SUPPLIES
Digital Power-Supply Voltage
Analog Power-Supply Voltage
Total Current for Digital and
Analog Supplies
Total Power-Down Current
V
DD
V
DDA
I
DC
I
PD
V
V
mA
µA
V
OH
V
OL
I
OH
= -4mA
I
OL
= 4mA
V
V
V
IH
V
IL
I
IH
, I
IL
V
OL
C
I
V
V
µA
V
pF
2
_______________________________________________________________________________________
Multiple-Output Clock Generators with
Dual PLLs and OTP
AC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DDA
= +3.0V to +3.6V, T
A
= -40°C to +25°C. Typical values are at V
DD
= V
DDA
= 3.3V, T
A
= +25°C with f
XTL
= 27MHz, unless
otherwise noted.) (Note 3)
PARAMETER
OUTPUT CLOCKS (CLK1, CLK2)
Minimum Frequency Range
Maximum Frequency Range
Clock Rise Time
Clock Fall Time
Duty Cycle
Output Period Jitter
J
P
f
OUT
f
OUT
t
R
t
F
f
IN
= 5MHz to 50MHz
f
IN
= 5MHz to 50MHz, C
L
< 5pF
20% to 80% of V
DD
, C
L
= 10pF,
f
OUT
= 74.1758MHz (Figure 5)
80% to 20% of V
DD
, C
L
= 10pF,
f
OUT
= 74.1758MHz (Figure 5)
f
OUT
= 74.1758MHz, C
L
= 10pF
125MHz, C
L
= 5pF, f
IN
= 27MHz
74.1758MHz, C
L
= 10pF,
f
IN
= 27MHz
SDA from low to high,
f
OUT
= 71.1758MHz, f
IN
= 13MHz
(Figure 6)
(Figure 6)
42
4
133
200
1.4
1.2
50
26.3
33.6
RMSps
58
MHz
MHz
ns
ns
%
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX9471/MAX9472
Soft Power-On Time
Hard Power-On Time
VCXO CLOCKS (CLK3, CLK4)
Crystal Frequency
Crystal Accuracy
Tuning Voltage Range
VCXO Tuning Range
TUNE Input Impedance
Output CLK Accuracy
Output Duty Cycle
Output Period Jitter
Output Rise Time
Output Fall Time
t
FST
t
PO1
f
XTL
V
TUNE
1
15
27
±30
0.0
3.0
±200
95
±50
40
50
36
1.4
1.4
60
ms
ms
MHz
ppm
V
ppm
kΩ
ppm
%
RMSps
ns
ns
V
TUNE
= 0 to 3V, C
1
= C
2
= 4.0pF
Z
TUNE
V
TUNE
= 1.5V, C
1
= C
2
= 4.0pF
C
L
= 10pF load, CLK3
C
L
= 10pF
t
R
t
F
20% to 80% of V
DD
(Figure 5),
C
L
= 10pF
80% to 20% of V
DD
(Figure 5),
C
L
= 10pF
±150
_______________________________________________________________________________________
3
Multiple-Output Clock Generators with
Dual PLLs and OTP
MAX9471/MAX9472
SERIAL-INTERFACE TIMING CHARACTERISTICS (MAX9471)
(V
DD
= V
DDA
= +3.3V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
Serial Clock
Bus Free Time Between STOP
and START Conditions
Hold Time, Repeated START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of SDA and SCL,
Receiving
Fall Time of SDA and SCL,
Receiving
Fall Time of SDA, Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each
Bus Line
SYMBOL
f
SCL
t
BUF
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
R
t
F
t
F,TX
t
SP
C
b
(Notes 3, 5)
(Notes 3, 5)
(Notes 3, 6)
(Notes 3, 7)
(Note 3)
(Note 4)
1.3
0.6
0.6
0.6
15
100
1.3
0.7
20 +
0.1C
b
20 +
0.1C
b
20 +
0.1C
b
0
300
300
250
50
400
900
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
pF
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level
voltage.
Note 3:
Guaranteed by design.
Note 4:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 5:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 6:
Bus sink current is less than 6mA. C
b
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between
0.3 x V
DD
and 0.7 x V
DD
.
Note 7:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
Multiple-Output Clock Generators with
Dual PLLs and OTP
MAX9471/MAX9472
Typical Operating Characteristics
(V
DD
= V
DDA
= +3.3V, T
A
= +25°C, f
XTL
= 27MHz, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9471/2 toc01
RISE TIME vs. TEMPERATURE
MAX9471/2 toc02
FALL TIME vs. TEMPERATURE
C
L
= 10pF
f
XTAL
= 27MHz
f
CLK1
= 66MHz
MAX9471/2 toc03
20
f
CLK1
= 125MHz
f
CLK2
= 74.1758MHz
2.2
16
SUPPLY CURRENT (mA)
1.8
RISE TIME (ns)
C
L
= 10pF
f
XTAL
= 27MHz
f
CLK1
= 66MHz
2.2
1.8
FALL TIME (ns)
12
1.4
1.4
8
1.0
1.0
4
0.6
0.6
0
-40
-15
10
35
60
85
TEMPERATURE (°C)
0.2
-40
-15
10
35
60
85
TEMPERATURE (°C)
0.2
-40
-15
10
35
60
85
TEMPERATURE (°C)
JITTER vs. TEMPERATURE
35
30
JITTER (ps)
25
20
15
10
5
0
-40
-15
10
35
60
85
f
CLK1
= 66MHz
f
CLK1
= 33MHz
CLK1
1V/div
C
L
= 10pF
f
XTAL
= 27MHz
MAX9471/2 toc04
33MHz OUTPUT
MAX9471/2 toc05
66MHz OUTPUT
MAX9471/2 toc06
40
CLK1
1V/div
10ns/div
10ns/div
TEMPERATURE (°C)
125MHz CLK OUTPUT
MAX9471/2 toc07
DUTY CYCLE vs. TEMPERATURE
MAX9471/2 toc08
VCXO TUNING RANGE
vs. VCXO ACCURACY
f
IN
= 27MHz
f
OUT
= 45MHz
4pF
5pF
100
0
-100
-200
-300
6pF
MAX9741/2 toc09
55
C
L
= 10pF
f
XTAL
= 27MHz
300
200
VCXO ACCURACY (PPM)
53
DUTY CYCLE (%)
CLK1
1V/div
51
f
CLK1
= 33MHz
49
47
f
CLK1
= 66MHz
45
4ns/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
VCXO TUNING RANGE (V)
_______________________________________________________________________________________
5
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