NB3L853141
2.5V/3.3V 1:5 LVPECL
Fanout Buffer
Description
The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L853141 features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The SEL pin will select the differential clock inputs, CLK0 &
CLK0, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When SEL is HIGH, the single−ended CLK1
input is selected.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced to the
negative edge of the clock input.
Features
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MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
A
WL
YY
WW
G
NB3L
3141
ALYW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
700 MHz Maximum Clock Output Frequency
•
CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL,
•
•
•
•
•
•
•
•
•
•
•
LVHSTL, SSTL, LVCMOS
CLK1 can Accept LVCMOS and LVTTL
Five Differential LVPECL Clock Outputs
1.5 ns Maximum Propagation Delay
Operating Range: V
CC
= 2.375 V to 3.8 V
LVCMOS Compatible Control Inputs
Selectable Differential or LVCMOS Clock Inputs
Synchronous Clock Enable
30 ps Max. Skew Between Outputs
−40°C to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
EN
D
Q
Q0
Q0
CLK0
CLK0
0
Q1
Q1
+
CLK1
1
Q2
Q2
Q3
SEL
Q3
Q4
Q4
Figure 1. Simplified Logic Diagram of
NB3L853141
ORDERING INFORMATION
Applications
•
Computing and Telecom
•
Routers, Servers and Switches
•
Backplanes
See detailed ordering and shipping information on page 8 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
December, 2015 − Rev. 2
Publication Order Number:
NB3L853141/D
NB3L853141
V
CC
20
EN
19
V
CC
NC CLK1 CLK0 CLK0 NC
18
17
16
15
14
13
SEL V
EE
12
11
Table 1. FUNCTION TABLE
CLK0
L
H
X
X
X
CLK1
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
*On next negative transition of CLK0 or CLK1
X = Don’t Care
1
Q0
2
Q0
3
Q1
4
Q1
5
Q2
6
Q2
7
Q3
8
Q3
9
Q4
10
Q4
Note: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Pinout
(Top View)
and Logic Diagram
Table 2. PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
VEE
SEL
NC
CLK0
CLK0
CLK1
NC
VCC
EN
VCC
Power
LVCMOS/LVTTL
Input
Power
Low
Multi−Level Input
Multi−Level Input
LVCMOS/LVTTL
Input
High
Low
Low
I/O
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
Power
LVCMOS / LVTTL
Input
Low
Open
Default
Description
Non−Inverted Differential Clock Output
Inverted Differential Clock Output
Non−Inverted Differential Clock Output
Inverted Differential Clock Output
Non−Inverted Differential Clock Output
Inverted Differential Clock Output
Non−Inverted Differential Clock Output
Inverted Differential Clock Output
Non−Inverted Differential Clock Output
Inverted Differential Clock Output
Negative Supply Voltage
Clock Select Input. When HIGH, selects CLK1 input. When LOW,
selects CLK0, CLK0 inputs. Internal Pull−down Resistor.
No Connect
Inverted Differential Clock Input. Internal Pull−up Resistor.
Non−Inverted Differential Clock Input. Internal Pull−down Resistor.
Single−ended Clock Input. Internal Pull−down Resistor.
No Connect
Positive Supply Voltage
Synchronous Clock Enable Input. When Low, outputs are enabled.
When High, outputs are disabled Low. Internal Pull−down Resistor.
Positive Supply Voltage
All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with
0.01
mF
to GND.
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2
NB3L853141
Table 3. ATTRIBUTES
(Note 1)
Characteristics
ESD Protection
R
PU
− Pull−up Resistor
R
PD
− Pull−down Resistor
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
TSSOP−20
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
50 kW
50 kW
Level 1
UL*94 code V*0 @ 0.125 in
300
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
LVPECL Mode Power Supply
LVPECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 260°C
TSSOP−20
TSSOP−20
TSSOP−20
Condition 1
V
EE
= 0 V
V
EE
= 0 V
Continuous
Surge
V
I
≤
V
CC
Condition 2
Rating
4.6
−0.5 to V
CC
+
0.5
50
100
−40 to +85
−65 to +150
140
50
23 to 41
265
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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NB3L853141
Table 5. DC CHARACTERISTICS
V
CC
= 2.375 V to 3.8 V; V
EE
= 0 V (Note 2); T
A
= −40°C to +85°C
Symbol
POWER SUPPLY
V
CC
I
EE
Power Supply Voltage
Power Supply Current (Outputs Open)
2.375
40
3.8
55
V
mA
Characteristic
Min
Typ
Max
Unit
LVPECL OUTPUTS
(Note 3)
V
OH
V
OL
V
SWING
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing, Peak−to−Peak
V
CC
−1.4
V
CC
−2.0
0.6
V
CC
−0.9
V
CC
−1.7
1.0
V
V
V
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Note 4) (Figures 3 and 4)
V
IH
V
IL
V
th
V
ISE
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 5)
Single−ended Input Voltage (V
IH
− V
IL
)
0.5
−0.3
0.35
0.3
V
CC
+0.3
V
CC
−1.0
V
CC
−0.85
V
CC
V
V
V
V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figures 5 and 6) (Note 6)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
Common Mode Input Voltage; (Note 7)
Input HIGH Current
Input LOW Current
V
CC
= V
IN
= 3.8 V CLK0
CLK0
V
CC
= 3.8V, V
IN
= 0 V CLK0
CLK0
−5
−150
0.5
0
0.15
0.5
V
CC
−0.85
V
IHD
−150
1.3
V
CC
–0.85
150
5
mA
mA
mV
mV
V
SINGLE−ENDED INPUTS (SEL, EN, CLK1)
V
IH
V
IL
I
IH
I
IL
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current VCC = V
IN
= 3.8 V
CLK1, SEL, EN
SEL, EN
CLK1
SEL, EN
CLK1
CLK1, SEL, EN
CLK1, SEL, EN
−5
2.0
2.0
−0.3
−0.3
V
CC
+0.3
V
CC
+0.3
0.8
V
CC
x0.35
150
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm.
2. Input and Output parameters vary 1:1 with V
CC
.
3. LVPECL outputs loaded with 50
W
to V
CC
− 2 V for proper operation.
4. V
th
, V
IH
, V
IL
, and V
ISE
parameters must be complied with simultaneously.
5. V
th
is applied to the complementary input when operating in single−ended mode.
6. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
7. The common mode voltage is defined as V
IH
.
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NB3L853141
Table 6. AC CHARACTERISTICS,
V
CC
= 2.375 V to 3.8 V, T
A
= −40°C to +85°C (Note 8)
Symbol
f
MAX
F
N
Characteristic
Maximum Input Clock Frequency: V
OUTpp
≥
400 mV
Phase Noise, f
C
= 155.52 MHz
CLK0/CLK0, V
INPPmin
≥
250 mV
CLK1
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Note 9
Note 10
Offset from Carrier
Min
700
300
−100.5
−128.2
−138.6
−147.1
−149.7
−154.2
−154.2
−154.2
0.8
0.8
1.0
1.0
0.05
30
150
150
200
45
45
1300
700
55
55
1.5
1.5
Typ
Max
Unit
MHz
dBc/
Hz
t
PLH
,
t
PHL
t
∫FN
tsk(o)
tsk (pp)
V
INpp
t
r
/t
f
ODC
Propagation Delay to Differential Outputs, @ 50 MHz
Additive Phase Jitter, RMS; f
C
= 155.52 MHz,
Integration Range: 12 kHz − 20 MHz
Output−to−output skew; (Note 11)
Part−to−Part Skew; (Note 12)
CLK0/CLK0 to Q/Q
CLK1 to Q
ns
ps
ps
ps
mV
ps
%
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14)
Output rise and fall times, 20% to 80%,
Output Clock Duty Cycle
Input Duty Cycle = 50%
Q, Q
CLK0/CLK0, f
≤
700 MHz, V
INPPmin
≥
250 mV
CLK1, f
≤
250MHz
All parameters measured at f
MAX
unless noted otherwise.
The cycle−to−cycle jitter on the input will equal the jitter on the
output. The part does not add jitter
8. Measured using a V
INPPmin
source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50
W
to V
CC
*
2 V.
9. Measured from the differential input crossing point to the differential output crossing point.
10. Measured from V
CC
/2 input crossing point to the differential output crossing point.
11. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points.
12. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same
type of inputs on each device, the outputs are measured at the differential cross points.
13. Output voltage swing is a single−ended measurement operating in differential mode.
14. Input voltage swing is a single−ended measurement operating in differential mode.
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