NCP1562A, NCP1562B
High Performance Active
Clamp/Reset PWM Controller
The NCP1562x is a family of voltage mode controllers designed
for dc- dc converters requiring high- efficiency and low parts count.
-
-
These controllers incorporate two in phase outputs with an overlap
delay to prevent simultaneous conduction and facilitates soft
switching. The main output is designed for driving a forward
converter primary MOSFET. The secondary output is designed for
driving an active clamp circuit MOSFET, a synchronous rectifier on
the secondary side, or an asymmetric half bridge circuit.
The NCP1562 family reduces component count and system size by
incorporating high accuracy on critical specifications such as
maximum duty cycle limit, undervoltage detector and overcurrent
threshold. Two distinctive features of the NCP1562 are soft- stop and
-
a cycle skip current limit with a time threshold. Soft- stop circuitry
-
powers down the converter in a controlled manner if a severe fault is
detected. The cycle skip detector enables a soft- stop sequence if a
-
continuous overcurrent condition is present.
Additional features found in the NCP1562 include line feed-
-
forward, frequency synchronization up to 1.0 MHz, cycle- by- cycle
- -
current limit with leading edge blanking (LEB), independent under
and overvoltage detectors, adjustable output overlap delay,
programmable maximum duty cycle, internal startup circuit and
soft- start.
-
Features
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MARKING
DIAGRAMS
16
1
TSSOP- 16
-
DT SUFFIX
CASE 948F
NCP
562x
ALYWG
G
SO- 16
-
D SUFFIX
CASE 751B
NCP1562xG
AWLYWW
Dual Control Outputs with Adjustable Overlap Delay
>2.0 A Output Drive Capability
Soft- Stop Powers Down Converter in a Controlled Manner
-
Cycle- by- Cycle Current Limit
- -
Cycle Skip Initiated if Continuous Current Limit Condition Exists
Voltage Mode Operation with Input Voltage Feedforward
Fixed Frequency Operation up to 1.0 MHz
Bidirectional Frequency Synchronization
Independent Line Undervoltage and Overvoltage Detectors
Accurate Programmable Maximum Duty Cycle Limit
Programmable Maximum Volt- Second Product
-
Programmable Soft- Start
-
Internal 100 V Startup Circuit
Precision 5.0 V Reference
These are Pb- Free Devices
-
x
A
WL, L
Y
WW, W
G or
G
= Current Limit (A, B)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-
-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 24 of this data sheet.
Typical Applications
Telecommunications Power Converters
Low Output Voltage Converters using Control Driven Synchronous
Rectifier
Industrial Power Converters
42 V Automotive System
ATX Power Supplies
Semiconductor Components Industries, LLC, 2010
November, 2010 - Rev. 5
1
Publication Order Number:
NCP1562A/D
NCP1562A, NCP1562B
1
V
in
16
C
AUX
V
AUX
+
--
V
AUX(on)
/
V
AUX(off1)
/
V
AUX(off2)
I
inhibit
I
start
Disable
V
AUX(on)
P.O.R.
Bias
Disable_VREF
S
Dominant
Reset Q
Latch
R
V
AUX
8
5.0 V Reference
V
REF
-
+
+
--
-
+
1V
One Shot
Pulse
Central
Logic
Thermal
Shutdown
V
in
R1
R2
2
UVOV
UVOV
Detector
V
UV
Soft--Stop
Complete
Enable_Output
V
AUX
15
OUT1
STOP
V
ref
R
T
3V
6
RTCT
7
SYNC
12
C
CSKIP
CSKIP
I
CSKIP(D)
+
--
4
CS
Clock
Soft--Stop
Complete
V
REF
10
C
SS
SS
I
SS(D)
Fixed 80 ns LEB
Enable
Soft--Start
Soft--Stop
Control Logic
0.2 V = A ver.
(0.5 V = B ver.)
OUT
Not
Saturated
I
CSKIP(C)
V
REF
CSKIP
Control
Logic
+
--
500
mA
Oscillator
DMAX
SYNC
Clock
Clock
CSKIP
Comparator
S
Q
Dominant
Reset
Latch
Q
R
Saturation
Comparator
14
Delay
Logic
V
AUX
13
OUT2
11
t
D
3.6 V
V
REF
20 kΩ
9
V
X
V
EA
270 kΩ
R
D
PGND
2V
C
T
+
-
V
CSKIP
FF Reset
+
-
Not
Saturated
+
--
-
+
Clock
Ilimit
Comparator
-
+
PWM
Comparator
Soft--Start
Comparator
- +
V
in
FF
Comparator
+
- +
--
0.2 V
3
FF
R
FF
I
SS(C)
STOP
V
X
Soft--Start
Complete
+
3V
--
C
FF
Enable_Output
FF Reset
5
GND
Figure 1. Detailed Block Diagram
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2
NCP1562A, NCP1562B
PIN FUNCTION DESCRIPTION
Pin
1
Symbol
V
in
Description
Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant
current source supplies current from this pin to the capacitor connected to the V
AUX
pin, eliminating the
need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.
Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used
for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).
The minimum and maximum input supply voltage thresholds are adjusted independently. A UV
condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage
exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain
3%
accuracy
allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.
An external R- divider from the input line generates the Feedforward Ramp. This ramp is used by the
-C
PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown
transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively
grounded until the next cycle begins.
Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converter
operates in cycle- -cycle current limit. Once a current limit pulse is detected, the cycle skip timer is
-by-
enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.
The leading edge blanking is disabled during soft-
-start and output overload conditions to improve the
response to faults.
Control circuit ground. All control and timing components that connect to GND should have the shortest
loop possible to this pin to improve noise immunity.
An external R
T
-
T
divider from V
REF
sets the operating frequency and maximum duty cycle of OUT1.
-C
The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is
generated by sequentially charging and discharging C
T
. The peak and valley of the Ramp are
accurately controlled to provide precise control of the duty cycle and frequency. The outputs are
disabled during the C
T
discharge time.
Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices to
synchronize together. The lower frequency device becomes the slave. It can also synchronize to an
external signal.
Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference
with a capacitor. The recommended capacitance range is between 0.047
mF
and 1.0
mF.
The error signal from an external error amplifier is fed to this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.
A 10
mA
current source charges the external capacitor connected to this pin. Duty cycle is limited
during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state
conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip fault
is detected, the SS capacitor is discharged in a controlled manner with a 100
mA
current source. The
duty cycle is then slowly reduced until reaching 0%.
An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2
transitions.
The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault
and the time the converter is disabled are programmed by the capacitor (C
CSKIP
) connected to this pin.
The cycle skip timer is enabled after a current limit fault is detected. Once enabled, C
CSKIP
is charged
with a 100
mA
source. If the overcurrent fault is removed before entering the soft-
-stop mode, the
capacitor is discharged with a 10
mA
source. Once C
CSKIP
reaches 3.0 V, the converter enters a
soft-
-stop mode and C
CSKIP
is discharged with a 10
mA
source. The converter is re-
-enabled once
C
CSKIP
reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, C
CSKIP
discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.
Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a
synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay
against OUT1. OUT2 has source and sink resistances of 12
Ω
(typ.). OUT2 is designed to handle up
to 1.0 A.
Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.
2
UVOV
3
FF
4
CS
5
6
GND
R
T
C
T
7
SYNC
8
9
V
REF
V
EA
10
SS
11
12
t
D
CSKIP
13
OUT2
14
PGND
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3
NCP1562A, NCP1562B
PIN FUNCTION DESCRIPTION
(continued)
Pin
15
Symbol
OUT1
Description
Main output of the PWM Controller. OUT1 has a source resistance of 4.0
Ω
(typ.) and a sink resistance
of 2.5
Ω
(typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to high
transition and leads OUT2 during a high to low transition.
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current
source supplies current from V
in
to this pin. Once the voltage on V
AUX
reaches approximately 10.3 V,
the current source turns OFF and the outputs are enabled. It turns ON again once V
AUX
falls to 8.0 V. If
the bias current consumption exceeds the startup current, V
AUX
will continue to discharge. Once V
AUX
reaches 7.0 V, the outputs are disabled allowing V
AUX
to charge. During normal operation, power is
supplied to the IC via this pin by means of an auxiliary winding. The startup circuit is disabled once the
voltage on the V
AUX
pin exceeds 10.3 V. If the V
AUX
voltage drops below 1.2 V (typ), the startup
current is reduced to 200
mA.
16
V
AUX
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4
NCP1562A, NCP1562B
MAXIMUM RATINGS
(Notes 1 and 2)
Rating
Line Voltage
Auxiliary Supply, OUT1, OUT2
All Other Inputs/Outputs Voltage
All Other Inputs/Outputs Current
5.0 V Reference Output Current
5.0 V Reference Output Voltage
OUT1 Peak Output Current (D = 2%)
OUT2 Peak Output Current (D = 2%)
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (T
A
= 25_C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
DT Suffix, Plastic Package Case 948F (TSSOP-
-16)
D Suffix, Plastic Package Case 751B (SO-
-16)
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
DT Suffix, Plastic Package Case 948F (TSSOP-
-16)
0.36 Sq In
1.0 Sq In
D Suffix, Plastic Package Case 751B (SO-
-16)
0.36 Sq In
1.0 Sq In
Symbol
V
in
V
AUX
, V
outx
V
IO
I
IO
I
REF
V
REF
I
out1
I
out2
T
J
T
stg
P
D
Value
100
20
10
5.0
10
-
-0.3 to 6.0
2.5
1.0
–40 to +125
–55 to +150
0.75
0.95
_C/W
155
133
120
105
Unit
V
V
V
mA
mA
V
A
A
_C
_C
W
R
θJA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 2-
-16:
Human Body Model 2000 V per MIL–STD–883, Method 3015.
Machine Model Method 160 V.
Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 100 V.
2. This device contains Latchup protection and exceeds
100
mA per JEDEC Standard JESD78.
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5
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