74LVC573A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED: t
PD
= 6.8ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for 1.65 to 3.6 V
CC
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
Figure 1: Pin Connection And IEC Logic Symbols
te
le
so
b
O
ro
P
uc
d
s)
t(
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
O
-
so
b
t
le
r
P
e
du
o
T&R
s)
t(
c
74LVC573AMTR
74LVC573ATTR
July 2004
Rev. 3
1/13
74LVC573A
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
3-State Latch Outputs
Table 3: Truth Table
INPUTS
OE
LE
GND
V
CC
Latch Enable Input
Ground (0V)
Positive Supply Voltage
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
O
te
le
so
b
O
Supply Voltage
I
OK
T
L
ro
P
uc
d
)-
(s
t
b
O
L
L
L
H
so
t
le
LE
X
L
H
H
r
P
e
D
X
X
L
H
du
o
s)
t(
c
Q
OUTPUT
Z
NO
CHANGE
L
H
X : Don’t Care
Z : High Impedance
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
DC Input Voltage
DC Output Voltage (V
CC
= 0V)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
I
CC
or I
GND
DC V
CC
or Ground Current per Supply Pin
Storage Temperature
T
stg
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
2/13
74LVC573A
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (V
CC
= 0V)
Output Voltage (High or Low State)
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7 to 3.0V)
High or Low Level Output Current (V
CC
= 2.3 to 2.7V)
High or Low Level Output Current (V
CC
= 1.65 to 2.3V)
Operating Temperature
Input Rise and Fall Time (note 2)
Parameter
Value
1.65 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
±
8
±
4
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
mA
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
-40 to 85 °C
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
OH
V
OL
et
l
so
b
O
P
e
ro
1.65 to 3.6
1.65
2.3
2.7
3.0
3.0
1.65 to 3.6
1.65
2.3
2.7
3.0
uc
d
)-
(s
t
I
O
=-100
µA
I
O
=-4 mA
I
O
=-8 mA
I
O
=-12 mA
I
O
=-18 mA
I
O
=-24 mA
I
O
=100
µA
I
O
=4 mA
I
O
=8 mA
I
O
=12 mA
I
O
=24 mA
V
I
= 0 to 5.5V
b
O
Min.
1.7
2
0.65V
CC
so
t
le
Max.
0.7
0.8
Value
r
P
e
Min.
0.65V
CC
1.7
2
du
o
Max.
s)
t(
c
mA
°C
ns/V
Unit
-55 to 125 °C
V
0.35V
CC
0.7
0.8
V
0.35V
CC
V
CC
-0.2
1.2
1.7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
±
5
10
±
5
V
CC
-0.2
1.2
1.7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
±
5
10
±
5
µA
µA
µA
V
V
Low Level Output
Voltage
I
I
I
off
I
OZ
Input Leakage Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
I
CC
incr. per Input
3.6
0
3.6
V
I
or V
O
= 5.5V
V
I
= V
IH
or V
IL
V
O
= 0 to 5.5V
V
I
= V
CC
or GND
I
CC
10
±
10
500
10
±
10
500
µA
µA
3/13
3.6
2.7 to 3.6
∆I
CC
V
I
or V
O
= 3.6 to
5.5V
V
IH
= V
CC
-0.6V
74LVC573A
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
Value
T
A
= 25 °C
Min.
Typ.
0.8
-0.8
Max.
V
Unit
V
OLP
V
OLV
Dynamic Low Level Quiet
Output (note 1)
1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Table 8: AC Electrical Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
2.7 to 3.6
C
L
(pF)
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
R
L
(Ω)
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
t
s
=
t
r
(ns)
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
-40 to 85 °C
Min.
Max.
TBD
TBD
7.8
6.8
TBD
TBD
7.8
6.8
TBD
TBD
8.7
7.7
TBD
TBD
7.6
7.0
Value
-55 to 125 °C
Min.
t
PLH
t
PHL
Propagation Delay
Time D to Q
1.5
1
t
PLH
t
PHL
Propagation Delay
Time LE to Q
t
PZL
t
PZH
Output Enable Time
t
PLZ
t
PHZ
Output Disable Time
te
le
so
b
O
t
W
LE Pulse Width
HIGH
t
s
t
h
t
OSLH
t
OSHL
ro
P
uc
d
s)
t(
O
-
so
b
1.5
1
1
1
t
le
r
P
e
1.5
1
1.5
1
du
o
Max.
TBD
TBD
9.4
8.2
TBD
TBD
9.4
8.2
TBD
TBD
10.4
9.2
TBD
TBD
9.1
8.4
s)
t(
c
Unit
ns
ns
1
1
ns
Setup Time D to LE,
(HIGH to LOW)
Hold Time LE (HIGH
to LOW) to D
2
2
TBD
TBD
3.3
3.3
TBD
TBD
2
2
TBD
TBD
1.5
1.5
2
2
TBD
TBD
3.3
3.3
TDB
TBD
2
2
TBD
TBD
1.5
1.5
ns
ns
ns
ns
Output To Output
Skew Time (note1,
2)
1
1
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
4/13
74LVC573A
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
Value
T
A
= 25 °C
Min.
f
IN
= 10MHz
Typ.
4
1.8
2.5
3.3
28
30
34
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
Figure 3: Test Circuit
R
T
= Z
OUT
of pulse generator (typically 50Ω)
Table 10: Test Circuit And Waveform Symbol Value
te
le
so
b
O
Symbol
C
L
R
L
= R
1
V
S
V
IH
V
M
V
OH
V
X
V
Y
t
r
= t
r
ro
P
30pF
1000Ω
2 x V
CC
V
CC
V
CC
/2
V
CC
uc
d
s)
t(
O
-
so
b
t
le
r
P
e
du
o
s)
t(
c
V
CC
2.3 to 2.7V
30pF
500Ω
2 x V
CC
V
CC
V
CC
/2
V
CC
V
OL
+ 0.15V
V
OH
- 0.15V
<2.0ns
2.7V
50pF
500Ω
6V
2.7V
1.5V
3.0V
V
OL
+ 0.3V
V
OH
- 0.3V
<2.5ns
3.0 to 3.6V
50pF
500Ω
7V
3.0V
1.5V
3.5V
V
OL
+ 0.3V
V
OH
- 0.3V
<2.5ns
1.65 to 1.95V
V
OL
+ 0.15V
V
OH
- 0.15V
<2.0ns
5/13
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