AS4C32M16D1
32M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Features
Fast clock rate: 200MHz
Differential Clock CK &
CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 8M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: V
DD &
V
DDQ
= 2.5V
±
0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
-
Pb and Halogen free
Advanced (Rev. 1.1, July / 2011)
Overview
The
512Mb DDR AS4C32M16D1 SDRAM
is a high-
speed CMOS double data rate synchronous DRAM
containing 512 Mbits. It is internally configured as a
quad 8M x 16 DRAM with a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CK). Data outputs occur at both rising edges of
CK and
CK
.d Read and write accesses to the SDRAM
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The DDR
SDRAM provides programmable Read or Write burst
lengths of 2, 4, or 8. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition,
The
DDR
AS4C32M16D1
features
programmable DLL option. By having a programmable
mode register and extended mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth and high
performance.
Table 1.Ordering Information
Temperature Temp Range
Part Number
Clock
Data Rate
Package
0 ~ 70°C
AS4C32M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial
Industrial
-40 ~ 85°C
AS4C32M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII
T: indicates TSOP II package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Confidential
1
Rev.1.1
July /2011
AS4C32M16D1
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Confidential
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Rev.1.1
July /2011
AS4C32M16D1
Figure 2. Block Diagram
CK
CK
CKE
DLL
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
8M x 16
CELL ARRAY
(BANK #0)
Column Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
8M x 16
CELL ARRAY
(BANK #1)
Column Decoder
A0
A9
A11
A12
BA0
BA1
LDQS
UDQS
DQ0
DQ15
~
~
ADDRESS
BUFFER
REFRESH
COUNTER
8M x 16
CELL ARRAY
(BANK #2)
Column Decoder
DATA
STROBE
BUFFER
DQ
Buffer
8M x 16
CELL ARRAY
(BANK #3)
Column Decoder
LDM
UDM
Alliance Memory Confidential
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Rev.1.1
July /2011
AS4C32M16D1
Pin Descriptions
Table 1. Pin Details
Symbol
CK,
CK
Type
Input
Description
Differential Clock:
CK and
CK
are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and negative
edge of
CK
. Input and output data is referenced to the crossing of CK and
CK
(both
directions of the crossing)
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs:
A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A9 with A10 defining
Auto Precharge).
Chip Select:
CS
enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when
CS
is sampled HIGH.
CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe:
The
RAS
signal defines the operation commands in
conjunction with the
CAS
and
WE
signals and is latched at the positive edges of CK.
When
RAS
and
CS
are asserted "LOW" and
CAS
is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the
WE
signal.
When the
WE
is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state. When the
WE
is asserted
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Column Address Strobe:
The
CAS
signal defines the operation commands in
conjunction with the
RAS
and
WE
signals and is latched at the positive edges of CK.
When
RAS
is held "HIGH" and
CS
is asserted "LOW," the column access is started
by asserting
CAS
"LOW." Then, the Read or Write command is selected by asserting
WE
"HIGH" or “LOW”.
Write Enable:
The
WE
signal defines the operation commands in conjunction with
the
RAS
and
CAS
signals and is latched at the positive edges of CK. The
WE
input
is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe:
Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
Data Input Mask:
Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Data I/O:
The DQ0-DQ15 input and output data are synchronized with positive and
negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
CKE
Input
BA0, BA1
A0-A12
Input
Input
CS
Input
RAS
Input
CAS
Input
WE
Input
LDQS,
UDQS
LDM,
UDM
DQ0 - DQ15
Input /
Output
Input
Input /
Output
Alliance Memory Confidential
4
Rev.1.1
July /2011
AS4C32M16D1
V
DD
V
SS
V
DDQ
V
SSQ
V
REF
NC
Supply
Supply
Supply
Supply
Supply
-
Power Supply:
2.5V
±
0.2V .
Ground
DQ Power:
2.5V
±
0.2V . Provide isolated power to DQs for improved noise immunity.
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Reference Voltage for Inputs:
+0.5*V
DDQ
No Connect:
These pins should be left unconnected.
Alliance Memory Confidential
5
Rev.1.1
July /2011
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