74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
December 2013
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
Features
■
5V tolerant inputs
■
2.3V–3.6V V
CC
specifications provided
■
5.2ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
■
Power down high impedance inputs and outputs
■
±24mA output drive (V
CC
=
3.0V)
■
Implements
proprietary
noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance:
General Description
The LCX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
200V
■
Leadless DQFN package
Ordering Information
Order Number
74LCX00M
74LCX00SJ
74LCX00BQX
(1)
74LCX00MTC
Package
Number
M14A
M14D
MLP14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Logic Symbol
IEEE/IEC
Pad Assignments for DQFN
(Top View)
(Bottom View)
Pin Description
Pin Names
A
n
, B
n
O
n
DAP
Description
Inputs
Outputs
No Connect
Note: DAP (Die Attach Pad)
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
2
74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
Supply Voltage
DC Input Voltage
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–50mA
–50mA
+50mA
±50mA
±100mA
±100mA
–65°C to +150°C
DC Output Voltage, Output in HIGH or LOW State
(2)
DC Input Diode Current, V
I
<
GND
DC Output Diode Current
V
O
<
GND
V
O
>
V
CC
I
O
I
CC
I
GND
T
STG
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
2. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
Operating
Data Retention
V
I
V
O
I
OH
/ I
OL
Input Voltage
Parameter
Min.
2.0
1.5
0
0
Max.
3.6
3.6
5.5
V
CC
±24
±12
±8
Units
V
V
V
mA
Output Voltage, HIGH or LOW State
Output Current
V
CC
=
3.0V–3.6V
V
CC
=
2.7V–3.0V
V
CC
=
2.3V–2.7V
T
A
∆
t /
∆
V
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
°C
ns / V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
3
74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
DC Electrical Characteristics
T
A
=
–40°C to +85°C
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
V
CC
(V)
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
2.7
3.0
Conditions
Min.
1.7
2.0
Max.
Units
V
0.7
0.8
I
OH
=
–100µA
I
OH
=
–8mA
I
OH
=
–12mA
I
OH
=
–18mA
I
OH
=
–24mA
I
OL
=
100µA
I
OL
=
8mA
I
OL
=
12mA
I
OL
=
16mA
I
OL
=
24mA
0
≤
V
I
≤
5.5V
V
I
or V
O
=
5.5V
V
I
=
V
CC
or GND
3.6V
≤
V
I
≤
5.5V
V
IH
=
V
CC
– 0.6V
V
CC
– 0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
10
10
±10
500
V
V
V
OL
LOW Level Output Voltage
2.3–3.6
2.3
2.7
3.0
V
I
I
I
OFF
I
CC
∆
I
CC
Input Leakage Current
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
2.3–3.6
0
2.3–3.6
2.3–3.6
µA
µA
µA
µA
AC Electrical Characteristics
T
A
=
–40°C to +85°C, R
L
=
500Ω
V
CC
=
3.3V ± 0.3V,
C
L
=
50pF
Symbol
t
PHL
, t
PLH
V
CC
=
2.7V,
C
L
=
50pF
Min.
1.5
V
CC
=
2.5V ± 0.2V,
C
L
=
30pF
Min.
1.5
Parameter
Propagation Delay
Min.
1.5
Max.
5.2
1.0
Max.
6.0
Max.
6.2
Units
ns
ns
t
OSHL
, t
OSLH
Output to Output Skew
(4)
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
4
74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Dynamic Switching Characteristics
T
A
=
25°C
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
V
CC
(V)
3.3
2.5
3.3
2.5
Conditions
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
Typical
0.8
0.6
–0.8
–0.6
Unit
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
Open, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10MHz
Typical
7
8
25
Units
pF
pF
pF
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
5
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