74LVC161
Presettable synchronous 4-bit binary counter; asynchronous
reset
Rev. 6 — 30 September 2013
Product data sheet
1. General description
The 74LVC161 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins
CP, PE, CET and CEP (thus providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by t
PHL
(propagation delay CP to TC) and t
su
(set-up time CEP to CP) according to the formula:
1
f
max
=
-----------------------------------
t
PHL
max
+
t
su
It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive edge-triggered clock
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
JESD8-C/JESD36 (2.7 V to 3.6 V)
Specified from
40 C
to +85
C
and
40 C
to +125
C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC161D
74LVC161DB
74LVC161PW
74LVC161BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
1
15
TC
3
4
5
6
9
D0
D1
D2
D3
PE
CEP CET
7
10
CP
2
MR
1
mna905
Q0
Q1
Q2
Q3
14
13
12
11
3
4
5
6
4 CT = 15
mna906
R
M1
G3
G4
CTR4
9
7
10
2
C2/1,3,4+
1,2D
14
13
12
11
15
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC161
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
2 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
3
D0
9
10
7
2
1
PE
CET
4
D1
5
D2
6
D3
PARALLEL LOAD
CIRCUITRY
TC
CEP
CP
MR
BINARY
COUNTER
15
Q0
14
Q1
13
Q2
12
Q3
mna907
11
Fig 3.
Functional diagram
0
15
14
13
12
1
2
3
4
5
6
7
11
10
9
8
mna908
Fig 4.
State diagram
74LVC161
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
3 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
5. Pinning information
5.1 Pinning
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
8
GND
PE
9
MR
2
3
4
5
6
7
1
CP
D0
D1
D2
D3
CEP
GND
3
4
14 Q0
13 Q1
D0
D1
D2
D3
6
7
8
001aad086
MR
CP
1
2
16 V
CC
15 TC
terminal 1
index area
161
5
12 Q2
11 Q3
10 CET
9
PE
161
GND
(1)
CEP
001aad087
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO16 and (T)SSOP16
Fig 6.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
MR
CP
D[0:3]
CEP
GND
PE
CET
Q[0:3]
TC
V
CC
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74LVC161
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
4 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
12
reset
preset
13
14
15
0
count
1
2
inhibit
mna909
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two;
inhibit.
Fig 7.
Timing sequence
74LVC161
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
5 of 22
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