Storage Temperature Range..............................-65°C to +160°C
Lead Temperature (soldering, 10s)..................................+300°C
Note 1:
The input voltage limits on PFI and WDI may be exceeded providing the input current is limited to less than 10mA.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
PARAMETER
Operating Voltage Range
Supply Current (MAX697)
(V
CC
= full operating range, V
BATT
= 2.8V, T
A
= +25°C, unless otherwise noted.)
CONDITIONS
MAX696 V
CC
T
A
= full
T
A
= full
I
OUT
= 1mA, T
A
= full
I
OUT
= 50mA, T
A
= full
I
OUT
= 250µA, V
CC
< (V
BATT
- 0.2V), T
A
= full
I
OUT
= 1mA
I
OUT
= 50mA
V
CC
= 0V, V
BATT
= 2.8V, T
A
= +25°C
V
CC
= 0V, V
BATT
= 2.8V, T
A
= full
5.5V > V
CC
> (V
BATT
+
0.3V)
T
A
= +25°C
T
A
= full
-100
-1.00
70
50
20
I
SINK
- 1.6mA
BATT ON = V
OUT
= 2.4V sink current
BATT ON = V
OUT
, V
CC
= 0V
V
CC
= +5V, +3V; T
A
= full
Figure 6, OSC SEL HIGH, V
CC
= 5V
Long period, V
CC
= 5V
Short period, V
CC
= 5V
0.5
1.25
35
1.00
70
7
2.5
1.30
50
1.6
100
25.0
1.35
70
2.25
140
0.4
V
CC
-
0.3
V
CC
-
0.5
V
BATT
-
0.1
MAX696 V
BATT
MAX697 V
CC
BATTERY-BACKUP SWITCHING (MAX696)
V
OUT
Output Voltage
V
OUT
in Battery-Backup Mode
Supply Current (Excludes I
OUT
)
Supply Current in Battery-Backup
Mode
Battery Standby Leakage Current
V
CC
-
0.1
V
CC
-
0.25
V
BATT
- 0.02
1.5
2.5
0.6
V
V
4
7
1
10
+20
+0.02
mA
µA
nA
µA
mV
mV
V
mA
µA
V
ms
s
ms
MIN
3.0
2.0
3.0
160
TYP
MAX
5.5
V
CC
- 0.3V
5.5
300
µA
V
UNITS
Battery Switchover Threshold V
CC
Power-up
- V
BATT
Power-down
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short-Circuit
Current
RESET AND WATCHDOG TIMER
Low-Line Voltage Threshold (LL
IN
)
Reset Timeout Delay
Watchdog Timeout Period,
Internal Oscillator
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Maxim Integrated │ 2
MAX696/MAX697
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
PARAMETER
Watchdog Timeout Period,
External Clock
Minimum WDI Input Pulse Width
RESET
and RESET Output
Voltage (Note 2)
LOW LINE
and
WDO
Output
Voltage
Output Short-Circuit Current
WDI Input Threshold
Long period
Short period
(V
CC
= full operating range, V
BATT
= 2.8V, T
A
= +25°C, unless otherwise noted.)
CONDITIONS
MIN
4032
960
200
0.4
0.4
3.5
0.4
3.5
1
3.5
3.8
20
-50
1.2
-15
1.3
±15
±0.01
MAX697
MAX696
I
SINK
= 1.6mA
I
SOURCE
= 1µA, V
CC
= 5V
V
PFI
= 0V, V
PFO
= 0V
V
IL
V
IH
, V
CC
= 5V
I
SINK
= 1.6mA
CE
OUT Output Voltage
CE
Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Frequency with External
Capacitor
V
OSC SEL
= 0V
V
OSC SEL
= 0V, C
OSC
= 47pF
0
4
±2
5
250
µA
µA
kHz
kHz
I
SOURCE
= 800µA
I
SOURCE
= 1µA, V
CC
= 0V
V
CC
= 5V
V
CC
- 0.5V
V
CC
- 0.05V
80
150
ns
3.0
3
0.4
V
3.5
1
3
25
0.8
-25
-500
±0.01
±0.01
1.4
±50
±25
+25
+25
0.4
50
µA
3
25
0.8
V
V
µA
V
TYP
MAX
4097
1025
UNITS
Clock
cycles
ns
V
IL
= 0.4V, V
IH
= 3.5V, V
CC
= 5V
I
SINK
= 400µA, V
CC
= 2V, V
BATT
= 0V
I
SINK
= 1.6mA, 3V < V
CC
< 5.5V
I
SOURCE
= 1µA, V
CC
= 5V
I
SINK
= 800µA, T
A
= full
I
SOURCE
= 1µA, V
CC
= 5V, T
A
= full
RESET,
RESET,
WDO, LOW LINE
V
CC
= 5V
(Note 3)
V
WDI
= V
OUT
V
WDI
= 0V
V
CC
= 3V, 5V
V
CC
= 3V, 5V
Logic-low
Logic-high (MAX696)
Logic-high (MAX697)
WDI Input Current
POWER-FAIL DETECTOR
PFI Input Threshold
PFI - LL
IN
Threshold Difference
PFI Input Current
LL
IN
Input Current
PFO
Output Voltage
PFO
Short-Circuit Source Current
CHIP-ENABLE GATING (MAX697)
CE
IN Thresholds
CE
IN Pullup Current
V
mV
nA
nA
V
µA
V
µA
Note 2:
T
A
= full operating range
Note 3:
WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and V
CC
is in the operating voltage range. WDI is
internally biased to 38% of V
CC
with an impedance of approximately 125kΩ.
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Maxim Integrated │ 3
MAX696/MAX697
Microprocessor Supervisory Circuits
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
MAX696
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
1.50
1.25
SUPPLY CURRENT (mA)
V
CC
MODE
1.00
0.75
0.50
0.25
0
1.50
1.25
SUPPLY CURRENT (µA)
BATTERY MODE
1.00
0.75
0.50
V
CC
MODE
BATTERY MODE
T
A
= 25°C
0.25
0
2
3
4
5
6
SUPPLY VOLTAGE (V)
MAX697
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
250
SUPPLY CURRENT (µA)
200
150
100
50
0
T
A
= +25°C
2
3
4
5
6
SUPPLY VOLTAGE (V)
300
250
RESET TIMEOUT DELAY
(ms)
200
150
100
50
0
RESET TIMEOUT DELAY AS A
FUNCTION OF SUPPLY VOLTAGE
T
A
= +25°C
2
3
4
5
6
SUPPLY VOLTAGE (V)
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Maxim Integrated │ 4
MAX696/MAX697
Microprocessor Supervisory Circuits
Pin Description
PIN
MAX696
1
2
3
4
MAX697
—
—
3
5
NAME
V
BATT
V
OUT
V
CC
GND
FUNCTION
Backup-Battery Input. Connect to ground if a backup battery is not used.
The higher of V
CC
or V
BATT
is internally switched to V
OUT
. Connect V
OUT
to V
CC
if
V
OUT
and V
BATT
are not used.
+5V Input
0V Ground Reference for All Signals
BATT ON goes High when V
OUT
is Internally Switched to the V
BATT
Input. It goes
low when V
OUT
is internally switched to V
CC
. The output typically sinks 7mA and
can directly drive the base of an external pnp transistor to increase the output current
above the 50mA rating of V
OUT
.
LOW LINE
goes Low when LL
IN
Falls Below 1.3V. It returns high as soon as LL
IN
rises above 1.3V. See Figure 5.
OSC IN Sets the Reset Delay Timing and Watchdog Timeout Period when OSC SEL
Floats or is Driven Low. The timing can also be adjusted by connecting an external
capacitor to this pin. See Figure 7. When OSC SEL is high, OSC IN selects between
fast and slow watchdog timeout periods
When OSC SEL is Unconnected or Driven High, the Internal Oscillator Sets the
Reset Time Delay and Watchdog Timeout Period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See
Table 1.
PFI is the Noninverting Input to the Power-Fail Comparator. When PFI is less than
1.3V, PFO goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
PFO
is the Output of the Power-Fail Comparator. It goes low when PFI is less than
1.3V. The comparator is turned off and
PFO
goes low when V
CC
is below V
BATT
.
The Watchdog Input, WDI, is a Three-Level Input. If WDI remains either high or low
for longer than the watchdog timeout period,
RESET
pulses low and
WDO
goes low.
The watchdog timer is disabled when WDI is left floating or is driven to mid-supply.
The timer resets with each transition at the watchdog timer input.
No Connection. Leave this pin open.
Low-Line Input. LL
IN
is the CMOS input to a comparator whose other input is a
precision 1.3V reference. The output is
LOW LINE
and is also connected to the reset
pulse generator. See Figure 2.
The Watchdog Output,
WDO,
goes Low if WDI Remains either High or Low for
Longer than the Watchdog Timeout Period.
WDO
is set high by the next transition at
WDI. If WDI is unconnected or at mid-supply,
WDO
remains high.
WDO
also goes
high when
LOW LINE
goes low.
RESET
goes Low whenever LL
IN
Falls Below 1.3V or V
CC
Falls Below the V
BATT
Input Voltage.
RESET
remains low for 50ms after LL
IN
goes above 1.3V.
RESET
also
goes low for 50ms if the watchdog timer is enabled but not serviced within its timeout
period. The
RESET
pulse width can be adjusted as shown in Table 1.
RESET is an Active-High Output. It is the inverse of
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