CY7C194B
CY7C195B
256 Kb (64K x 4) Static RAM
Features
• Fast access time: 12 ns, 15 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ
General Description
1
The CY7C194B-CY7C195B is a high-performance CMOS
Asynchronous SRAM organized as 64K × 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected. Output enable (OE) is
supported only in CY7C195B.
2
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28
DIP, and 28 SOJ package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
(7C195 only)
X
A
X
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best-practice recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only.
15 ns
15
80
10
25 ns
25
80
10
Unit
ns
mA
mA
12
90
10
Cypress Semiconductor Corporation
Document #: 38-05409 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised September 17, 2003
CY7C194B
CY7C195B
Pin Layout and Specifications
CY7C195B 28 DIP (6.9 × 35.6 × 3.5 mm) – P21
NC
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
CY7C195B 28 SOJ (8 × 18 × 3.5 mm) – V21
NC
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
Document #: 38-05409 Rev. *A
Page 2 of 13
CY7C194B
CY7C195B
Pin Layout and Specifications
(continued)
CY7C194B 24 SOJ (8 × 15 × 3.5 mm) – V13
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
I/O
3
I/O
2
I/O
1
I/O
0
WE
CY7C194B 24 DIP (6.6 × 31.8 × 3.5 mm) – P13
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
I/O
3
I/O
2
I/O
1
I/O
0
WE
Document #: 38-05409 Rev. *A
Page 3 of 13
CY7C194B
CY7C195B
Pin Description
Pin
A
X
Type
Input
Address Inputs.
Description
28 DIP
2, 3, 4, 5, 6,
7, 8, 9, 10,
11, 22, 23,
24, 25, 26,
27
12
16, 17, 18,
19
1, 20, 21
13
28
15
24 DIP
1, 2, 3, 4, 5,
6, 7, 8, 9,
10, 18, 19,
20, 21, 22,
23
11
14, 15, 16,
17
–
–
24
13
24 SOJ
1, 2, 3, 4, 5,
6, 7, 8, 9,
10, 18, 19,
20, 21, 22,
23
11
14, 15, 16,
17
–
–
24
13
28 SOJ
2, 3, 4, 5, 6,
7, 8, 9, 10,
11, 22, 23,
24, 25, 26,
27
12
16, 17, 18,
19
1, 20, 21
13
28
15
CE
I/O
X
NC
OE
V
CC
WE
Control
Input or
Output
–
Control
Supply
Control
Chip Enable.
Data Input/Outputs.
No Connect.
Pins are not internally connected to
the die.
Output Enable (CY7C195 only).
Power (5.0V).
Write Enable.
CY7C195B Truth Table
CE
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
I/Ox
High Z
Data Out
Data In
High Z
Mode
Deselect / Power-Down
Read
Write
Selected, outputs disabled
Power
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
CY7C194B Truth Table
CE
H
L
L
WE
X
H
L
Input/Output
High Z
Data Out
Data In
Mode
Power-Down
Read
W rite
Power
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Document #: 38-05409 Rev. *A
Page 4 of 13
CY7C194B
CY7C195B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Parameter
T
STG
T
AMB
V
CC
V
CC
I
OUT
V
ESD
I
LU
Storage Temperature
Ambient Temperature with Power Applied (i.e. case temperature)
Core Supply Voltage Relative to V
SS
DC Voltage Applied to any Pin Relative to V
SS
Output Short-Circuit Current
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Latch-up Current
Description
Value
–65 to +150
–55 to +125
–0.5 to +7.0
–0.5 to V
CC
+ null
20
> 2001
> 200
Unit
°C
°C
V
V
mA
V
mA
Operating Range
Range
Commercial
Ambient Temperature (T
A
)
0°C to 70°C
Voltage Range (V
CC
)
5.0V ± 10%
DC Electrical Characteristics
3
12 ns
Parameter
V
IH
V
IL
V
OH
V
OL
I
CC
I
SB1
I
SB2
I
OZ
I
IX
Description
Input HIGH Volt-
age
Input LOW Volt-
age
Output HIGH Volt- V
CC
= Min., loh = -4.0 ma
age
Output LOW Volt- V
CC
= Min., lol = 8.0 ma
age
V
CC
Operating
Supply Current
V
CC
= Max., I
OUT
= 0 mA, f =
F
MAX
= 1 / t
RC
Condition
Min
2.2
–0.3
2.4
–
–
–
Max
V
CC
+
0.3
0.8
–
0.4
90
30
2.2
–0.3
2.4
–
–
–
15 ns
Min
Max
V
CC
+
0.3
0.8
–
0.4
80
30
2.2
–0.5
2.4
–
–
–
25 ns
Min
Max
V
CC
+
0.3
0.8
–
0.4
80
30
Unit
V
V
V
V
mA
mA
Automatic CE
V
CC
= Max., CE
≥
V
IH
, V
IN
≥
V
IH
Power-down Cur- or V
IN
≤
V
IL
, f = F
MAX
rent TTL Inputs
Automatic CE
V
CC
= Max., CE
≥
V
CC
- 0.3v,
Power-down Cur- V
IN
> V
CC
- 0.3v or V
IN
≤
0.3,f
rent CMOS Inputs = 0 Commercial
Output Leakage
Current
Input Load Cur-
rent
GND
≤
Vi
≤
V
CC
, Output Dis-
abled
GND
≤
Vi
≤
V
CC
–
10
–
10
–
10
mA
–5
–5
+5
+5
–5
–5
+5
+5
–5
–5
+5
+5
uA
uA
Capacitance
4
Max
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Conditions
T
A
= 25C, f = 1 MHz,
V
CC
= 5.0V
ALL - PACKAGES
7
10
Unit
pF
Notes:
3. V
IL
(min) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05409 Rev. *A
Page 5 of 13
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