CD4029BC Presettable Binary/Decade Up/Down Counter
October 1987
Revised January 1999
CD4029BC
Presettable Binary/Decade Up/Down Counter
General Description
The CD4029BC is a presettable up/down counter which
counts in either binary or decade mode depending on the
voltage level applied at binary/decade input. When binary/
decade is at logical “1”, the counter counts in binary, other-
wise it counts in decade. Similarly, the counter counts up
when the up/down input is at logical “1” and vice versa.
A logical “1” preset enable signal allows information at the
“jam” inputs to preset the counter to any state asynchro-
nously with the clock. The counter is advanced one count
at the positive-going edge of the clock if the carry in and
preset enable inputs are at logical “0”. Advancement is
inhibited when either or both of these two inputs is at logi-
cal “1”. The carry out signal is normally at logical “1” state
and goes to logical “0” state when the counter reaches its
maximum count in the “up” mode or the minimum count in
the “down” mode provided the carry input is at logical “0”
state.
All inputs are protected against static discharge by diode
clamps to both V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
s
Low power TTL compatibility:
or 1 driving 74LS
s
Parallel jam inputs
s
Binary or BCD decade up/down counting
3V to 15V
fan out of 2 driving 74L
0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4029BCWM
CD4029BCSJ
CD4029BCN
Package Number
M16B
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005960.prf
www.fairchildsemi.com
CD4029BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
(Note 2)
700 mW
500 mW
−0.5V
to
+18
V
DC
−0.5V
to V
DD
+
0.5 V
DC
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
3V to 15 V
DC
0V to V
DD
V
DC
−40°C
to
+85°C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device Current
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OL
LOW Level
Output Voltage
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OH
HIGH Level
Output Voltage
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current (Note 3)
I
OH
HIGH Level Output
Current (Note 3)
I
IN
Input Current
Conditions
−40°C
Min
Max
20
40
80
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.3
0.3
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
4.95
9.95
14.95
Min
+25°C
Typ
Max
20
40
80
0
0
0
5
10
15
1.5
3.0
4.0
0.05
0.05
0.05
+85°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
Units
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1V or 9V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1V or 9V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−5
10
−5
−0.3
0.3
0.36
0.9
2.4
−0.36
−0.9
−2.4
−1.0
1.0
µA
µA
Note 3:
I
OH
and I
OL
are tested one output at a time.
3
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CD4029BC
AC Electrical Characteristics
Symbol
CLOCKED OPERATION
t
PHL
or t
PLH
Propagation Delay Time
to Q Outputs
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
Parameter
(Note 4)
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
L
=
15 pF
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
285
120
95
100
50
40
160
70
55
15
10
5
180
70
55
1.5
3.7
4.5
3.1
7.4
9
5
65
285
115
95
400
165
135
80
30
25
150
60
50
265
110
90
200
85
70
570
230
195
800
330
260
160
60
50
300
120
100
530
220
180
400
170
140
7.5
360
140
110
570
240
190
200
100
80
320
135
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
MHz
MHz
MHz
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Typ
Max
Units
T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200k, Input t
rCL
=
t
fCL
=
20 ns, unless otherwise specified
200
85
70
320
135
110
400
170
140
640
270
220
ns
ns
ns
ns
ns
ns
t
THL
or t
TLH
Transition Time/Q
or Carry Output
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
WH
or t
WL
Minimum Clock
Pulse Width
t
rCL
or t
fCL
Maximum Clock Rise
and Fall Time
t
SU
Minimum Set-Up Time
f
CL
Maximum Clock Frequency
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
IN
C
PD
t
PHL
or t
PLH
Average Input Capacitance
Power Dissipation Capacitance
Propagation Delay Time
to Q output
Any Input
Per Package (Note 5)
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
PRESET ENABLE OPERATION
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
t
WH
Minimum Preset Enable
Pulse Width
t
REM
Minimum Preset Enable
Removal Time
CARRY INPUT OPERATION
t
PHL
or t
PLH
Propagation Delay Time
to Carry Output
t
PHL
, t
PLH
Propagation Delay Time
to Carry Output
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
L
=
15 pF
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Note 4:
*AC Parameters are guaranteed by DC correlated testing.
Note 5:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
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