SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5261. Input data is latched on the
rising edge of the serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5261. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5261. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when address-
ing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5261.
R
H
, R
L
: Resistor End Points
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
:
Wiper
The R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT5261 and
CS
high disables the CAT5261.
CS
high takes the SO output pin to
high impedance and forces the devices into a Standby mode (unless an internal write operation is underway). The CAT5261
draws ZERO current in the Standby mode. A high to low transition on
CS
is required prior to any sequence being initiated. A low to
high transition on
CS
after a valid write sequence is what initiates an internal write cycle.
WP:
Write Protect
WP
WP
is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
WP
is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed).
WP
going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated,
WP
going low will have no
effect on any write operation.
HOLD
Hold
HOLD:
The
HOLD
pin is used to pause transmission to the CAT5261 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause,
HOLD
must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.)
HOLD
may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2122, Rev. B
2
CAT5261
SERIAL BUS PROTOCOL
The CAT5261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5261 to interface directly with many
of today's popular microcontrollers. The CAT5261
contains an 8-bit instruction register .The instruction set
and the operation codes are detailed in the instruction
set table 3 on page 9.
After the device is selected with
CS
going low the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. The
first byte contains one of the six op-codes that define the
operation to be performed.
DEVICE OPERATION
The CAT5261 is two resistor arrays integrated with an
SPI serial interface logic, two 8-bit wiper control registers
and eight 8-bit, non-volatile memory data registers.
Each resistor array contains 255 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R
W
) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
3
Document No. 2122, Rev. B
CAT5261
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)(2)
................ -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current .................................................... +6mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Recommended Operating Conditions:
V
CC
= +2.5V to +6.0V
Temperature
Industrial
Min
-40°C
Max
85°C
Notes:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output
pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(2)
Relative Linearity
(3)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
w(n)(actual)
-R
(n)(expected)(5)
R
w(n+1)
-[R
w(n)+LSB
]
(5)
(1)
(1)
(1)
R
POT
= 50kΩ
(1)
10/10/25
0.4
+300
20
I
W
= +3mA @ V
CC
=3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
(1)
0.4
+1
+0.2
GND
200
100
25°C, each pot
1
50
+3
300
150
V
CC
%
mW
mA
Ω
Ω
V
nV/ Hz
%
LSB
(4)
LSB
(4)
ppm/°C
ppm/°C
pF
MHz
Test Conditions
Min
Typ
100
50
+20
Max
Units
kΩ
kΩ
%
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
(5) n = 0, 1, 2, ..., 255
Document No. 2122, Rev. B
4
CAT5261
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OH1
Parameter
Power Supply Current
Power Supply Current
Non-Volatile WRITE
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output High Voltage
Test Conditions
f
SCK
= 2.5MHz, SO Open
V
CC
= 6 V Inputs = GND
f
sck
= 2.5MHz, SO Open
V
CC
= 6 V, Inputs = GND
V
IN
= GND or V
CC;
SO Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
1
5
1
10
10
Units
mA
mA
µA
µA
µA
V
V
V
V
-1
V
CC
x 0.7
I
OL
= 3 mA
I
OH
= -1.6mA
V
CC
-0.8
V
CC
x 0.3
V
CC
+ 1.0
0.4
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
= 25˚C, f = 1.0 MHz, V
CC
= 5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD,
A0, A1)
Min
Typ
Max
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
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