WS128K32-XXX
128Kx32 SRAM MODULE, SMD 5962-93187
FEATURES
n
Access Times of 70, 85, 100, 120ns
n
MIL-STD-883 Compliant Devices Available
n
Packaging
66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400).
68 lead, 40mm Low Profile CQFP, 3.56mm
(0.140")(Package 502).
68 lead, Hermetic CQFP (G2U), 22.4mm
(0.880 inch) square, 4.57mm (0.140 inch)
high, (Package 510)
68 lead, Hermetic CQFP (G1U), 23.9mm
(0.940 inch) square, 4.57mm (0.140inch) high,
(Package 519)
n
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
n
Commercial, Industrial and Military Temperature
Ranges
n
5 Volt Power Supply
n
Low Power CMOS
n
TTL Compatible Inputs and Outputs
n
Built in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation
n
Weight
WS128K32-XG1U - 5 grams typical
WS128K32-XG2UX - 8 grams typical
WS128K32-XH1X - 13 grams typical
WS128K32-XG4TX - 20 grams typical
n
All devices are upgradeable to 512Kx32
4
SRAM MODULES
FIG. 1
PIN CONFIGURATION FOR WS128K32N-XH1X
TOP VIEW
PIN DESCRIPTION
34
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
7
A
12
NC
A
13
A
8
I/O
16
I/O
17
I/O
18
44
V
CC
CS
4
WE
4
I/O
27
A
4
A
5
A
6
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
66
56
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
NC
I/O
0
I/O
1
I/O
2
11
12
WE
2
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
NC
I/O
3
22
23
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
September 2001 Rev. 3
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS128K32-XXX
FIG. 2
PIN CONFIGURATION FOR WS128K32-XG4TX
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-16
WE
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
CS
1
CS
2
CS
3
CS
4
4
SRAM MODULES
WE
OE
A
0
-
16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
FIG. 3
PIN CONFIGURATION FOR WS128K32-XG1UX
AND WS128K32-XG2UX
TOP VIEW
PIN DESCRIPTION
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
2
WS128K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Read
Out Disable
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
4.5
2.2
-0.5
Max
5.5
V
CC
+ 0.3
+0.8
Unit
V
V
V
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G4T
CQFP G1U
CQFP G2U
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max
50
20
50
20
15
20
20
50
Unit
pF
pF
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
pF
pF
pF
4
SRAM MODULES
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
ILI
ILO
ICC
ISB
VOL
Conditions
VCC = 5.5, VIN = GND to VCC
CS = VIH, OE = VIH, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5
CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5
Min
-70
Max
10
10
120
20
0.4
Min
-85
Max
10
10
120
20
0.4
Min
-100
Max
10
10
120
20
0.4
Min
-120
Max
10
10
120
20
0.4
Units
µA
µA
mA
mA
V
V
IOL = 2.1mA, Vcc = 4.5
2.4
VOH IOH = -1.0mA, Vcc = 4.5
2.4
2.4
2.4
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS
(T
A
= -55°C to +125°C)
Parameter
Data Retention
Supply Voltage
Data Retention
Current
Symbol
Conditions
-70
Min Max
2.0
5.5
4
-85
Min Max
2.0
5.5
4
-100
Min Max
2.0
5.5
4
-120
Min Max
2.0
5.5
4
Units
V
DR
I
CCDR1
CS³V
CC
-0.2V
V
CC
= 3V
V
mA
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS128K32-XXX
AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55°C To +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
3
0
25
25
3
70
35
3
0
25
25
Symbol
Min
70
70
3
85
45
3
0
35
35
-70
Max
Min
85
85
3
100
50
3
0
35
35
-85
Max
Min
100
100
3
120
60
-100
Max
Min
120
120
-120
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
1. This parameter is guaranteed by design but not tested.
4
SRAM MODULES
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55°C To +125°C)
Symbol
Min
70
60
60
30
50
5
5
5
25
0
0
-70
Max
Min
85
75
75
35
55
5
5
5
25
0
-85
Max
Min
100
80
80
40
70
5
5
5
35
0
-100
Max
Min
120
100
100
50
80
5
5
5
35
-120
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
t
OW
1
t
WHZ
1
t
DH
1. This parameter is guaranteed by design but not tested.
FIG. 4
AC TEST CONDITIONS
Parameter
Input Pulse Levels
I
OL
Current Source
AC TEST CIRCUIT
Typ
VIL = 0, VIH = 3.0
Unit
V
ns
V
V
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
5
1.5
1.5
D.U.T.
C
eff
= 50 pf
V
Z
1.5V
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75W.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
4
WS128K32-XXX
FIG. 5
TIMING WAVEFORM - READ CYCLE
FIG. 6
4
SRAM MODULES
WRITE CYCLE - WE CONTROLLED
FIG. 7
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
WC
WS32K32-XHX
t
CW
t
AH
t
AS
CS
t
AW
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
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