CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
1 K / 2 K × 8 Dual-port Static RAM
1 K / 2 K × 8 Dual-port Static RAM
Features
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Functional Description
CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static
RAMs. Two ports are provided permitting independent access to
any location in memory. The CY7C131E / CY7C131AE /
CY7C136E / CY7C136AE can be used as a standalone dual-port
static RAM. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. The BUSY flag signals that the port
is trying to access the same location, which is currently being
accessed by the other port. The INT is an interrupt flag indicating
that data is placed in a unique location
[1]
. The BUSY and INT
flags are push pull outputs. An automatic power-down feature is
controlled independently on each port by the chip enable (CE)
pins.
The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
1 K / 2 K × 8 organization
0.35 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
High speed access: 15 ns
Low operating power: I
CC
= 110 mA (typical),
Standby: I
SB3
= 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
BUSY output flag to indicate access to the same location by
both ports
INT flag for port-to-port communication
Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin
plastic quad flat package (PQFP)
Pb-free packages available
Logic Block Diagram
R/
WL
CE
L
OE
L
R/
WR
CE
R
OE
R
I/O
7L
I/O
0L
[2]
BUSY
L
A
9/10L
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
[2]
BUSY
R
ADDR
DECODER
MEMORY
ARRAY
ADDR
DECODER
A
9/10R
[4]
A
0R
[4]
A
0L
CE
L
OE
L
R/
WL
7C131E/7C131AE/
ARBITRATION
7C136E/7C136AE
LOGIC
ARBITRATION LOGIC
(7C130/7C131 ONLY)
INTERRUPT LOGIC
AND
INTERRUPT LOGIC
CE
R
OE
R
R/
WR
[3]
INT
L
[3]
INT
R
Notes
1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.
2. BUSY is a push-pull output. No pull-up resistor required.
3. INT: push-pull output. No pull-up resistor required.
4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.
Cypress Semiconductor Corporation
Document Number: 001-64231 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 15, 2012
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Selection Guide ................................................................ 3
Maximum Ratings............................................................. 4
Operating Range............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
AC Test Loads and Waveforms ....................................... 5
Switching Characteristics ................................................ 6
Switching Characteristics ................................................ 8
Switching Waveforms .................................................... 10
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Document Number: 001-64231 Rev. *D
Page 2 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Pin Configurations
Figure 1. Pin Diagram - 52-pin PLCC (Top View)
[5]
A0L
OEL
NC/A10L
INT
L
BUSYL
R/W
L
CEL
VCC
CER
R/W
R
[5]
BUSY
R
INTR
NC/A10R
[5]
A0L
OEL
NC/A10L
INT
L
BUSYL
R/W
L
CEL
VCC
CER
R/W
R
Figure 2. Pin Diagram - 52-pin PQFP (Top View)
[5]
BUSY
R
INTR
NC/A10R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131E/7C131AE
40
7C136E/7C136AE
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O 4L
I/O 5L
I/O 6L
I/O 7L
NC
GND
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
52 51 50 49 48 47 46 45 44 43 42 41 40
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
7C131E/7C131AE
7C136E/7C131AE
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
9/10L[5]
I/O
0L
–I/O
7L
INT
L
BUSY
L
V
CC
GND
CE
R
R/W
R
OE
R
A
0R
–A
9/10R[5]
I/O
0R
–I/O
7R
INT
R
BUSY
R
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output
Interrupt Flag
Busy Flag
Power
Ground
Description
Selection Guide
Parameter
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
(both ports TTL level)
Typical Standby Current for I
SB3
(Both ports CMOS level)
7C131E-15
7C131AE-15
15
110
50
0.05
7C131E-25
7C136E-25
25
100
45
0.05
7C131E-55
7C136E-55
7C136AE-55
55
95
45
0.05
Unit
ns
mA
mA
mA
Note
5. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.
Document Number: 001-64231 Rev. *D
I/O5R
I/O6R
I/O 4L
I/O 5L
I/O 6L
I/O 7L
Page 3 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
DC input voltage
[8]
.......................................–0.5 V to +7.0 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... >1100 V
Latch up current ..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings
[6]
may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied .......................................... –55
C
to +125
C
Supply voltage to ground potential ..............–0.3 V to +7.0 V
DC voltage applied to outputs
in High Z State .............................................–0.5 V to +7.0 V
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
C
to +70
C
–40
C
to +85
C
V
CC
5 V ± 10%
5 V ± 10%
Electrical Characteristics
Over the Operating Range
7C131E-15
7C131AE-15
7C131E-25
7C136E-25
7C131E-55
7C136E-55
Unit
7C136AE-55
Max Min Typ
[9]
Max
–
2.4
–
V
0.4
–
0.8
–
2.2
–
–
–
–
–
0.8
+20
0.4
V
V
V
A
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
I
SB1
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Output
Leakage
Current
V
CC
Operating
Supply Current
Standby
Current,
Both Ports,
TTL Inputs
Standby
Current,
One Port,
TTL Inputs
Standby
Current,
Both Ports,
CMOS Inputs
Standby
Current,
One Port,
CMOS Inputs
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 4.0 mA
Min Typ
[9]
Max Min Typ
[9]
2.4
–
–
2.4
–
–
2.2
–
–
–
–
–
0.4
–
0.8
+20 –20
2.2
–
–
–
–
GND < V
O
< V
CC
,
Output disabled
V
CC
= Max, I
OUT
= 0 mA
Outputs disabled
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
CE
L
or CE
R
> V
IH
,
Active Port Outputs
Open,
f = f
MAX[7]
Both Ports
CE
L
and CE
R
> V
CC
–
0.2 V,
V
IN
> V
CC
– 0.2 V
or V
IN
< 0.2 V, f = 0
One Port
CE
L
or CE
R
> V
CC
– 0.2
V,
V
IN
> V
CC
– 0.2 V
or V
IN
< 0.2 V,
Active Port Outputs Open,
f = f
MAX[7]
Commercial
Industrial
Commercial
Industrial
–20
+20 –20
–
–
110
115
50
65
190
200
70
95
–
–
100
110
45
65
170
180
65
95
–
–
95
105
45
65
160
170
65
95
mA
mA
I
SB2
Commercial
Industrial
–
120
135
180
205
–
110
135
160
205
–
110
135
160
205
mA
I
SB3
Commercial
Industrial
–
0.05
0.05
0.5
0.5
–
0.05
0.05
0.5
0.5
–
0.05
0.05
0.5
0.5
mA
I
SB4
Commercial
Industrial
–
110
125
160
175
–
100
125
140
175
–
100
125
140
175
mA
Notes
6. The voltage on any I/O pin cannot exceed the power pin during power-up.
7. At f = f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3 V.
8. Pulse width < 20 ns.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
(typ.), T
A
= 25 °C.
Document Number: 001-64231 Rev. *D
Page 4 of 19
CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
Capacitance
[10]
Parameter
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 5.0 V
Max
15
10
Unit
pF
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
5V
R1 = 893
OUTPUT
C = 30 pF
R2 = 347
OUTPUT
C = 30 pF
V
TH
= 1.4 V
R
TH
= 250
R1 = 893
OUTPUT
C = 5 pF
R2 = 347
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
including scope and jig)
ALL INPUT PULSES
3.0 V
GND
10%
90%
(CY7C131E/CY7C131AE ONLY)
90%
10%
5
ns
5 ns
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-64231 Rev. *D
Page 5 of 19
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