LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
DESCRIPTION
The
LF2249
is a high-speed digital
mixer comprised of two 12-bit
multipliers and a 24-bit accumulator.
All multiplier inputs are user acces-
sible, and each can be updated on
every clock cycle. The LF2249 utilizes
a pipelined architecture with fully
registered inputs and outputs and an
asynchronous three-state output
enable control for optimum flexibility.
Independent input register clock
enables allow the user to hold the
data inputs over multiple clock cycles.
Each multiplier input also includes a
user-selectable 1-16 clock pipeline
delay. The output of each multiplier
can be independently negated under
user control for subtraction of prod-
ucts. The sum of the products can
also be internally rounded to 16 bits
during the accumulation process.
A separate 16-bit input port con-
nected to the accumulator is included
to allow cascading of multiple
LF2249s. Access to all 24 bits of the
accumulator is gained by switching
between upper or lower 16-bit words.
The accumulated output data is
updated on every clock cycle.
All inputs and outputs of the LF2249
are registered on the rising edge of
clock, except for OE. Internal pipeline
registers for all data and control
inputs are provided to maintain
FEATURES
u
40 MHz Data and Computation Rate
u
Two 12 x 12-bit Multipliers with
Individual Data Inputs
u
Separate 16-bit Input Port for
Cascading Devices
u
Independent, User-Selectable 1–16
Clock Pipeline Delay for Each Data
Input
u
User-Selectable Rounding of Products
u
Fully Registered, Pipelined
Architecture
u
Three-State Outputs
u
Fully TTL Compatible
u
Replaces TRW/Raytheon/Fairchild
TMC2249
u
120-pin PQFP
1
2
3
4
5
6
LF2249 B
LOCK
D
IAGRAM
ADEL
3-0
A
11-0
ENA
BDEL
3-0
B
11-0
ENB
CDEL
3-0
C
11-0
ENC
DDEL
3-0
D
11-0
END
7
8
1–16
1–16
1–16
1–16
9
4
NEG
2
CLK
NEG
1
4
10
RND
4
2's COMP
2's COMP
4
ACC
11
FT
16
3
CASEN
2:1
16
24
CAS
15-0
MS
1
16
0
0
16
1
LS
SWAP
2:1
2:1
OE
16
NOTE: NUMBERS IN REGISTERS INDICATED
NUMBER OF PIPELINE DELAYS.
S
15-0
Video Imaging Products
1
08/16/2000–LDS.2249-J
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
D
ETAILED
V
IEW OF
B
LOCK
D
IAGRAM
O
UTLINED
A
REA
ADEL
3-0
4
A
11-0
12
ENA
synchronous operation between the
incoming data and all available
control functions. The LF2249 oper-
ates at a clock rate of 40 MHz over the
full commercial temperature and
supply voltage ranges.
Because of its flexibility, the LF2249 is
ideally suited for applications such as
image switching and mixing, digital
quadrature mixing and modulating,
FIR filtering, and arithmetic function
and waveform synthesis.
R
1
R
2
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
A
11-0
–D
11-0
— Data Inputs
A
11-0
–D
11-0
are 12-bit data input regis-
ters. Data is latched into the input reg-
isters on the rising edge of CLK. The
contents of the input registers are
clocked into the top of the correspond-
ing 16-stage pipeline delay (pushing the
contents of the register stack down one
register position) on the next clock cycle
if the pipeline register stack is enabled.
The LSBs are A
0
-D
0
(Figure 1a).
CAS
15-0
— Cascade Data Input
CAS
15-0
is the 16-bit cascade data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is CAS
0
(Figure 1a).
16 : 1
12
CLK
R
16
F
IGURE
1
A
.
I
NPUT
F
ORMATS
Data Input
11 10 9 8 7 6 5 4 3 2 1 0
–2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
(Sign)
Cascade Input
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
(Sign)
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
Sum Output (Upper 16 bits)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
(Sign)
Sum Output (Lower 16 bits)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
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08/16/2000–LDS.2249-J
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
NEG
1
–NEG
2
— Negate Control
ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging products are
added to the sum of the previous prod-
ucts.
RND — Rounding Control
When RND is HIGH, the sum of the
products of the data being input on
the current clock cycle will be
rounded to 16 bits. To avoid the accu-
mulation of roundoff errors, round-
ing is only performed during the first
cycle of each accumulation process.
SWAP — Output Select
The SWAP control allows the user to
access all 24 bits of the accumulator
output by switching between upper
and lower 16-bit words. When SWAP
is HIGH, the upper 16 bits of the accu-
mulator are always output. When
SWAP is LOW, the lower 16 bits of the
accumulator are output on every
other clock cycle. As long as SWAP
remains LOW, new output data will
not be clocked into the output regis-
ters.
OE — Output Enable
When the OE signal is LOW, the
current data in the output registers
is available on the S
15-0
pins. When
OE is HIGH, the outputs are in a
high-impedance state.
Outputs
S
15-0
— Data Output
The NEG
1
and NEG
2
controls deter-
mine whether a subtraction or accumu-
The current 16-bit result is available
lation of products is performed. When
on the S
15-0
outputs. The output data
NEG
1
is HIGH, the product
A x B
is
may be either the upper or lower 16
negated, causing the product to be sub-
bits of the accumulator output, de-
tracted from the accumulator contents.
pending on the state of SWAP. The
Likewise, when NEG
2
is HIGH, the
LSB is S
0
(Figure 1b).
product
C x D
is negated, causing the
product to be subtracted as well. NEG
1
and NEG
2
determine the operation to
Controls
be performed on the data input during
ENA–END — Pipeline Register Enable
the current clock cycle when ADEL–
Input data in the
N
(
N
= A, B, C, or D) DDEL = 0000.
input register is latched into the corre-
sponding pipeline register stack on
CASEN — Cascade Enable
each rising edge of CLK for which EN
N
is LOW. Data already in the
N
register When CASEN is LOW, data being in-
stack is pushed down one register posi- put on the CAS
15-0
inputs during that
tion. When EN
N
is HIGH, the data in clock cycle will be registered and accu-
the
N
pipeline register stack does not mulated internally. When CASEN is
change, and the data in the
N
input HIGH, the CAS
15-0
inputs are ignored.
register will not be stored in the register
stack.
FT — Feedthrough Control
When FT is LOW and ADEL–DDEL =
0000, data being input on the CAS
15-0
inputs is delayed three clock cycles to
N
DEL (
N
= A, B, C, or D) is the 4-bit align the data with the data being input
registered pipeline delay select word. on the A
11-0
–D
11-0
inputs. When FT is
N
DEL determines which stage of the
N
HIGH, the cascade data being input is
pipeline register stack is routed to the routed around the three delay registers
multiplier inputs. The minimum delay to simplify the cascading of multiple
is one clock cycle (
N
DEL = 0000), and devices.
the maximum delay is 16 clock cycle
(
N
DEL = 1111). Upon power up, the
values of ADEL–DDEL and the con-
tents of the pipeline register stacks are
unknown and must be initialized by the
user.
ADEL
3-0
–DDEL
3-0
— Pipeline Delay
Select
1
2
3
4
5
6
7
8
9
10
11
Video Imaging Products
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08/16/2000–LDS.2249-J
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V
CC
+ 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to V
CC
+ 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
C
IN
C
OUT
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
Input Capacitance
Output Capacitance
(Note 3)
Test Condition
Vcc
= Min.,
I
OH
= –2.0 mA
Vcc
= Min.,
I
OL
= 4.0 mA
Min
2.4
Typ
Max
Unit
V
0.4
2.0
0.0
V
CC
0.8
±10
±40
100
6
10
10
V
V
V
µA
µA
mA
mA
pF
pF
Ground
≤
V
IN
≤
V
CC
(Note 12)
(Note 12)
(Notes 5, 6)
(Note 7)
T
A
= 25°C, f = 1 MHz
T
A
= 25°C, f = 1 MHz
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08/16/2000–LDS.2249-J
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*D
ISCONTINUED
S
PEED
G
RADE
Symbol
Symbol
*Assumes ADEL–DDEL = 0000
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Min
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5 2 9
1
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Min
DEVICES INCORPORATED
S
WITCHING
W
AVEFORMS
M
ILITARY
O
PERATING
R
ANGE
(–55°C to +125°C)
Notes 9, 10 (ns)
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
t
DIS
t
ENA
t
D
t
H
t
S
t
PWH
t
PWL
t
CYC
t
DIS
t
ENA
t
D
t
H
t
S
t
PWH
t
PWL
t
CYC
CONTROLS
(Except OE)
A
11-0
– D
11-0
S
15-0
*
OE
CLK
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Hold Time
Input Setup Time
Clock Pulse Width, HIGH
Clock Pulse Width, LOW
Cycle Time
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Hold Time
Input Setup Time
Clock Pulse Width, HIGH
Clock Pulse Width, LOW
Cycle Time
Parameter
t
S
N
1
t
H
N+1
t
PWH
2
t
PWL
N+2
t
DIS
3
5
HIGH IMPEDANCE
10
40
15
t
ENA
0
8
40*
Max
15
15
17
t
D
6
Video Imaging Products
12 x 12-bit Digital Mixer
Min
10
40
10
33
15
15
0
0
8
8
S
N
LF2249-
33
40*
7
Max
Max
15
15
17
15
15
15
LF2249-
S
N + 1
Min
Min
10
33
10
25
15
10
08/16/2000–LDS.2249-J
0
0
8
7
33*
LF2249
25
8
S
N + 2
Max
Max
15
15
15
15
15
14
11
10
9
8
7
6
5
4
3
2
1
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