LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
DESCRIPTION
The
LF3304
is a dual line buffer/
FIFO, designed to operate at HDTV
rates. The LF3304 will operate in
two distinct modes: Line Buffer and
FIFO. In these modes the two memo-
ries can operate independently or
with common control.
The LF3304 comprises two 12-bit 4K
memories configurable in a variety of
ways including: Two 12-bit 4K deep
line buffers (independent lengths),
Three 8-bit 4K deep line buffers
(common lengths), One 12-bit 8K
deep line buffer, or Two 12-bit 4K
FIFOs (independent operation).
In FIFO mode, independent Read
and Write Resets give the designer
control over the internal pointers
providing flexibility not commonly
found in ordinary FIFOs.
The LF3304 operatates at a maximum
data rate of 100 MHz and is available
in a 100-lead PQFP package.
FEATURES
u
100 MHz Data Rate for Video and
other High-Speed Applications
u
One 24-bit, Two 12-bit, Three
8-bit Data Paths, or One Double
Depth 12-bit
u
Dual Modes: Line Buffer or FIFO
u
User-Programmable FIFO Flags
u
User-Resettable Read and Write
Pointers
u
Single 3.3 V Power Supply,
5 V Tolerant I/O
u
100-lead PQFP
LF3304 B
LOCK
D
IAGRAM
WCLKA
RCLKA
WENA
RENA
RRA
RWA
RAM ARRAY 1
CONTROL
FLAG
GENERATOR
FFA
EFA
PAFA
PAEA
OEA
12
AIN
11-0
VARIABLE LENGTH RAM ARRAY A
4K x 12-bit
12
AOUT
11-0
ADDRA
LDA
12
LENGTH
11-0
ADDRB
LDB
MASTER
CONTROL
VARIABLE LENGTH RAM ARRAY B
12
BIN
11-0
12
BOUT
11-0
4K x 12-bit
OEB
2
MODE
1-0
WCLKB
RCLKB
WENB
RENB
RRB
RWB
RAM ARRAY 2
CONTROL
FLAG
GENERATOR
FFB
EFB
PAFB
PAEB
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
the data presented on LENGTH
11-0
is
loaded into the device on the active edge of
WCLKA in conjunction with LDA being
driven LOW. To set the length of RAM
Array B the data presented on
LENGTH
11-0
is loaded into the device
on the active edge of WCLKB in
conjunction with LDB being driven
LOW. If an equal length is desired for
both RAM Arrays, the data presented
on LENGTH
11-0
is loaded into the
device on the active edge of WCLK
(WCLKA and WCLKB tied together) in
conjuction with LDx (LDA and LDB
tied together) being driven LOW.
MODE
1-0
— Mode Select
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
Controls
LDA — RAM Array A Load
When LDA is LOW, data on
LENGTH
11-0
is latched in the length
register on the rising edge of xCLKA.
LDB — RAM Array B Load
When LDB is LOW, data on
LENGTH
11-0
is latched in the length
register on the rising edge of xCLKB.
WENA — Write Enable A
LINE BUFFER MODE
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must
be connected.
Clocks
WCLKA — Write Clock A
WCLKA and RCLKA must be tied
together for RAM Array A to properly
operate as a Line Buffer. The rising edge
of xCLKA strobes all appropriate
enabled registers.
RCLKA — Read Clock A
See WCLKA description.
WCLKB — Write Clock B
WCLKB and RCLKB must be tied
together for RAM Array B to properly
operate as a Line Buffer. The rising
edge of xCLKB strobes all appropriate
enabled registers.
RCLKB — Read Clock B
See WCLKB description.
Inputs
AIN
11-0
— Data Input
A
AIN
11-0
is the 12-bit registered data
input port.
BIN
11-0
— Data Input
B
BIN
11-0
is the 12-bit registered data
input port.
LENGTH
11-0
— Line Buffer Length
The 12-bit value is used to specify the
length of each of the RAM Arrays. An
integer value ranging from 0 to 4095 is
used to select a delay ranging from 2 to
4097 clock cycles. The value placed on
LENGTH
11-0
is equal to the desired delay
minus 8. To set the length of RAM Array A
T
ABLE
1. D
EVICE
C
ONFIGURATION
MODE
1-0
0
0
1
1
0
1
0
1
Mode Select
Dual Line Buffer
Cascaded Line Buffer
Dual FIFO
Reserved
delay mode, RWA and RRA should be
brought LOW to properly reset the Write
and Read pointers.
RENA — Read Enable B
In Line Buffer mode, RENA must be
kept LOW.
WENB — Write Enable B
Driving WENB LOW places the device in
programmable delay mode and driving
WENB HIGH places RAM Array B in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed
while data on BIN
11-0
is ignored. When
switching back from recirculate mode to
delay mode, RWB and RRB should be
brought LOW to properly reset the Write
and Read pointers.
RENB — Read Enable B
In Line Buffer mode, RENB must be
kept LOW.
RWA — Reset Write A
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
RRA — Reset Read A
The read address pointer is reset to the
first physical location when RRA is set
LOW. After power up, the LF3304
requires a Reset Read for initialization
because the read address pointer is not
defined at that time.
Driving WENA LOW places the device in
programmable delay mode and driving
WENA HIGH places RAM Array A in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed while
data on AIN
11-0
is ignored. When
switching back from recirculate mode to
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
Clocks
WCLKA — Write Clock A
Data present on AIN
11-0
is written
into the LF3304 on the rising edge of
WCLKA when the device is configured
for writing.
RCLKA — Read Clock A
Data is read from the LF3304 and
presented on the output port (AOUT
11-0
)
after
t
D
has elapsed from the rising
edge of RCLKA when the device is
configured for reading and the output
port is enabled. WCLKA and RCLKA
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
WCLKB — Write Clock B
BIN
11-0
— Data Input
B
BIN
11-0
is the 12-bit registered data
input port.
ADDRA — Address A
If LDA is LOW, on the rising edge of
WCLKA data present on AIN
11-0
is
written into the PAFA or PAEA register
depending on ADDRA (see Table 2).
The LSB, AIN
0
, corresponds to the LSB
of PAFA and PAEA registers. The MSB,
AIN
11
, corresponds to the MSB of PAFA
and PAEA registers.
ADDRB — Address B
If LDB is LOW, on the rising edge of
WCLKB data present on BIN
11-0
is
written into the PAFB or PAEB register
depending on ADDRB (see Table 2).
The LSB, BIN
0
, corresponds to the LSB
of PAFB and PAEB registers. The MSB,
BIN
11
, corresponds to the MSB of PAFB
and PAEB registers.
MODE
1-0
— Mode Select
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
LENGTH — Non-Flag Pins
In FIFO Mode, the unused LENGTH pins
(LENGTH
11
, LENGTH
10
, LENGTH
5
,
LENGTH
4
) must be tied LOW.
Controls
Operation
PAEA Register
PAFA Register
PAEB Register
PAFB Register
RWB — Reset Write B
See RWA Description.
RRB — Reset Read B
See RRA description.
OEA — Output Enable A
When OEA is LOW, AOUT
11-0
is
enabled for output. When OEA is
HIGH, AOUT
11-0
is placed in a high-
impedence state.
OEB — Output Enable B
When OEB is LOW, BOUT
11-0
is
enabled for output. When OEB is
HIGH, BOUT
11-0
is placed in a high-
impedence state.
Outputs
AOUT
11-0
— Data Output A
AOUT
11-0
is the 12-bit registered
data output port.
BOUT
11-0
— Data Output B
BOUT
11-0
is the 12-bit registered
data output port.
Data present on BIN
11-0
is written into
the LF3304 on the rising edge of
WCLKB when the device is configured
for writing.
RCLKB — Read Clock B
Data is read from the LF3304 and
presented on the output port (BOUT
11-0
)
after
t
D
has elapsed from the rising
edge of RCLKB when the device is
configured for reading and the output
port is enabled. WCLKB and RCLKB
can be tied together and driven by the
same external clock or they may be
controlled by separate external clocks.
Inputs
AIN
11-0
— Data Input
A
AIN
11-0
is the 12-bit registered data
input port.
FIFO MODE
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must be
connected.
T
ABLE
2. L
OADING
P
ROGRAMMABLE
F
LAG
R
EGISTERS
ADDRA
0
1
x
x
ADDRB
x
x
0
1
LDA
0
0
x
x
LDB
x
x
0
0
x
x
WCLKA
WCLKB
x
x
LDA — RAM Array A Load
When LDA is LOW, data on AIN
11-0
is
latched in the LF3304 on the rising edge
of WCLKA.
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
RRA — Reset Read A
The read address pointer is reset to the first
physical location when RRA is set LOW.
After power up, the LF3304 requires a Reset
Read for initialization because the read
address pointer is not defined at that time.
RWB — Reset Write B
See RWA Description.
RRB — Reset Read B
See RRA description.
OEA — Output Enable A
When OEA is LOW, AOUT
11-0
is
enabled for output. When OEA is
HIGH, AOUT
11-0
is placed in a high-
impedence state. The flag outputs are
not affected by OEA.
OEB — Output Enable B
When OEB is LOW, BOUT
11-0
is
enabled for output. When OEB is
HIGH, BOUT
11-0
is placed in a high-
impedence state. The flag outputs are
not affected by OEB.
Outputs
AOUT
11-0
— Data Output A
LOW, read operations can not be
performed. The Empty Flag is synchro-
nized to the rising edge of RCLKA.
FFB — Full Flag B
FFB goes LOW when RAM Array B is full
of data. When FFB is LOW, RAM Array B
can not be written to. The Full Flag is
synchronized to the rising edge of WCLKB.
EFB — Empty Flag B
EFB goes LOW when the read pointer
is equal to the write pointer, indicating
that RAM Array B is empty. When EFB
is LOW, read operations can not be
performed. The Empty Flag is synchro-
nized to the rising edge of RCLKB.
PAFA—ProgrammableAlmost-FullFlagA
PAFA goes LOW when the write
pointer is (Full – N) locations ahead of
the read pointer. N is the value stored
in the PAFA register and has no default
value. PAFA is synchronized to the
rising edge of WCLKA.
PAEA—ProgrammableAlmost-EmptyFlagA
PAEA goes HIGH when the write
pointer is (N + 1) location ahead of the
read pointer. N is the value stored in
the PAEA register and has no default
value. PAEA is synchronized to the
rising edge of RCLKA.
PAFB—ProgrammableAlmost-FullFlagB
PAFB goes LOW
when
the write pointer
is (Full – N) locations ahead of the read
pointer. N is the value stored in the
PAFB register and has no default value.
PAFB is synchronized to the rising
edge of WCLKB.
PAEB—ProgrammableAlmost-EmptyFlagB
PAEB goes HIGH when the write
pointer is (N + 1) location ahead of the
read pointer. N is the value stored in
the PAEB register and has no default
value. PAEB is synchronized to the
rising edge of RCLKB.
LDB — RAM Array B Load
When LDB is LOW, data on BIN
11-0
is
latched in the LF3304 on the rising
edge of WCLKB.
WENA — Write Enable A
If WENA is LOW, data on AIN
11-0
is
written to the device on the rising edge
of WCLKA. When RAM Array A is
full, WENA is ignored.
RENA — Read Enable A
If RENA is LOW, data from RAM Array
A is read and presented on AOUT
11-0
after
t
D
has elapsed from the rising
edge of RCLKA if the output port is
enabled. If RENA goes HIGH, the last
value loaded in the RAM Array A
output register will remain unchanged.
When RAM Array A is empty, RENA is
ignored.
WENB — Write Enable B
If WENB is LOW, data on BIN
11-0
is
written to the device on the rising edgle
of WCLKB. When RAM Array B is full,
WENB is ignored.
RENB — Read Enable B
If RENB is LOW, data from RAM Array
B is read and presented on BOUT
11-0
after tD has elapsed from the rising
edge of RCLKB if the output port is
enabled. If RENB goes HIGH, the last
value loaded in the RAM Array B
output register will remain unchanged.
When RAM Array B is empty, RENB is
ignored.
RWA — Reset Write A
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
AOUT
11-0
is the 12-bit registered data
output port.
BOUT
11-0
— Data Output B
BOUT
11-0
is the 12-bit registered data
output port.
FFA — Full Flag A
FFA goes LOW when RAM Array A is
full of data. When FFA is LOW, RAM
Array A can not be written to. The Full
Flag is synchronized to the rising edge
of WCLKA.
EFA — Empty Flag A
EFA goes LOW when the read pointer is
equal to the write pointer, indicating that
RAM Array A is empty. When EFA is
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LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
should be disregarded. For example,
as the 4096th data word is written
into the FIFO, assuming that no
preceding read cycles have occured,
FFx will be driven LOW thus indicat-
ing a ‘full’state. While the FIFO is
still in this ‘full’ state, the next
enabled write will access address
000H, thus writing over data that
has not yet been read out.
Flag Enable Reset
A Flag Enable Reset resets the read
and write pointers and enables the
flags to control the reading and
writing of data according to the Full
Flag and Empty Flag conditions. A
Flag Enable Reset occurs when the
following conditions are met:
1.
2.
3.
RWA/RWB must be LOW for at
least one WCLKA/WCLKB cycle.
RRA/RRB must be LOW for at
least one RCLKA/RCLKB cycle.
WENx and RENx must be HIGH
during the above two conditions
plus one addition write or read
cycle (which ever is longer).
2.
Flag Disable Reset
A Flag Disable Reset resets the read
and write pointers and disables the
flags from controlling the reading
and writing of data. A Flag Disable
Reset occurs when the following
conditions are met:
1.
RWA/RWB must be LOW for at
least one WCLKA/WCLKB cycle
while WENx is LOW.
RRA/RRB must be LOW for at
least one RCLKA/RCLKB cycle
while RENx is LOW.
FIFO MODE
OPERATION
Initialization
Upon power-up, the LF3304 requires
the initialization of the internal read
and write address pointers. This
initialization sequence can be done
by either a Flag Enable Reset or a
Flag Disable Reset.
A Flag Enable Reset will force the
FIFO to operate in a ‘Flag Enabled’
mode. In this mode, writing will be
disabled when FFx is LOW and
reading is disabled when EFx is
LOW. Any ‘write beyond full’ event
or ‘read beyond empty’ event will be
disabled. Note: in an ‘empty’ state,
the last data word read from the
FIFO is held on the output bus until
the next valid read cycle.
A Flag Disable Reset will force the
FIFO to operate in a ‘Flag Disabled’
mode. In this mode, the user is
allowed to write over previously un-
read data and read out previously
read data. Consequently, any
enabled write or read is valid thus
allowing the write and read pointers
to ‘wrap-around’. Note: due to the
nature of this mode, the flag status
Configuration of Programmable Flags
In order to load a FIFO A Program-
mable Flag Register, a rising edge of
WCLKA, while WENA is LOW,
latches AIN11-0 into either the PAFA
or PAEA Register - depending on the
states of ADDRA and LDA (See
Table 2).
In order to load a FIFO B Program-
mable Flag Register, a rising edge of
WCLKB, while WENB is LOW,
latches BIN11-0 into either the PAFB
or PAEB Register - depending on the
states of ADDRB and LDB (See Table
2). See the Figure labeled “Program-
mable Flag Load Timing.”
The Flag Enable Reset condition can
be disabled if one of the two Flag
Disable Reset conditions are applied.
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