1024MB Fully Buffered DIMM Server Memory Module
CM72FB1024-XXX
Key Features
240-pin, Fully Buffered dual in-line memory module (FB-DIMM)
Ultra high density using 512 MBit SDRAM devices
CRC and ECC error detection and correction
Advanced Memory Buffer (AMB)
128 MB x 72
JEDEC standard1.5V high speed differential point-to-point link
Four-bit prefetch architecture
Off-chip driver (OCD) impedance calibration
On-die termination (ODT)
Low profile (1.2”), ideal for 1U rack mount servers
Selection Guide
CM72FB1024-XXX
MODULE SIZE:
1024 MByte
SPEED (XXX):
533: DDR2-533 (6.3 GB/s)
667: DDR2-667 (8.0 GB/s)
Page 1
1024MB Fully Buffered DIMM Server Memory Module
General Description
The CM72FB1024 is a DDR2 Fully Buffered Dual Inline Memory Module (FB-DIMM),
designed for applications in which both per-formance and density are critical. This
DIMM includes Error Checking and Correcting (ECC) for maximum reliability, and has
an Advanced Memory Buffer (AMB) for data, address and control signals to enable fully
configured systems. These modules are constructed using 512 MBit SDRAMs, and are
fully compliant with JEDEC specifications.
These DIMMs are constructed using 64MB x 4 SDRAMs in BGA packages. The
module also includes an EEPROM to support Serial Presence Detect (SPD)
requirements. Decoupling capacitors are mounted on the printed circuit board for each
SDRAM device, and On-Die Termination is provided on all lines. The synchronous
design of these Corsair SDRAM DIMMs allows precise cycle control with the use of the
system clock. I/O transactions are possible on every clock cycle. The high clock
frequency and high density of this device enable a high level of performance to be
achieved in advanced workstations and servers.
Page 2
1024MB Fully Buffered DIMM Server Memory Module
Pin Description
Pin Name
SCK
/SCK
PN[13:0]
/PN[13:0]
PS[9:0]
/PS[9:0]
SN[13:0]
/SN[13:0]
SS[9:0]
/SS[9:0]
SCL
SDA
SA[2:0]
VID[1:0]
/RESET
RFU
VCC
VDD
VTT
VDDSPD
VSS
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered
DIMMs VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value:
OPEN = 1.5 V, GND = 1.2 V
AMB reset signal
Reserved for Future Use
AMB Core Power and AMB Channel Interface Power (1.5 Volt)
DRAM Power and AMB DRAM I/O Power (1.8 Volt)
DRAM Address/Command/Clock Termination Power (VDD/2)
SPD Power
Ground
The DNU/M_Test pin provides an external connection on R/Cs A-D for testing the
margin of Vref which is produced by a voltage divider on the module. It is not
intended to be used in normal system operation and must not be connected (DNU)
in a system. This test pin may have other features on future card designs and if it
does, will be included in this specification at that time.
Total
Note:
Pin Description
Count
1
1
14
14
10
10
14
14
10
10
1
1
3
2
1
16
8
24
4
1
80
2
Note
1
1
DNU/M_Test
1
1
240
<1>
System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.
<2>
Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility.
Page 4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
