nonvolatile, read/write storage solution for a wide
range of applications. The LH28F160BG-TL/
BGH-TL can operate at V
CC
and V
PP
= 2.7 V.
Their low voltage operation capability realizes
longer battery life and suits for cellular phone
application. Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F160BG-TL/BGH-TL offer two levels of
protection : absolute protection with V
PP
at GND,
selective hardware boot block locking. These
alternatives give designers ultimate control of their
code security needs.
16 M-bit (1 MB x 16) Smart 3
Flash Memories
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM-compatible write interface
• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Thirty-one 32 k-word main blocks
– Top or bottom boot location
• Enhanced cycling capability
– 100 000 block erase cycles
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I
CC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOX
TM
∗
V nonvolatile flash technology
• Packages
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend/Reverse bend
– 60-ball CSP (FBGA060/048-P-0811)
∗
ETOX is a trademark of Intel Corporation.
COMPARISON TABLE
VERSIONS
LH28F160BG-TL
LH28F160BGH-TL
LH28F160BV-TL
∗
BIT CONFIGURATION
1 MB x 16
1 MB x 16
2 MB x 8/1 MB x 16
2 MB x 8/1 MB x 16
OPERATING TEMPERATURE
0 to +70°C
–25 to +85°C
0 to +70°C
–40 to +85°C
LH28F160BVH-TL
∗
∗
Refer to the datasheet of LH28F160BV-TL/BVH-TL.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
P
• Smart 3 technology
– 2.7 to 3.6 V V
CC
– 2.7 to 3.6 V or 12 V V
PP
• High performance read access time
LH28F160BG-TL10/BGH-TL10
– 100 ns (2.7 to 3.6 V)
LH28F160BG-TL12/BGH-TL12
– 120 ns (2.7 to 3.6 V)
R
E
L
FEATURES
IM
-1-
IN
A
R
Y
LH28F160BG-TL/BGH-TL
PIN CONNECTIONS
48-PIN TSOP (Type I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
RY/BY#
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TOP VIEW
A
16
NC
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE#
GND
CE#
A
0
(TSOP048-P-1220)
NOTE :
Reverse bend available on request.
60-BALL CSP
1
A NC
B
IM
2
3
4
5
NC
A
14
A
11
A
8
WE#
WP#
A
17
A
5
A
13
A
10
NC
RP#
V
PP
A
18
A
6
A
3
NC
A
2
IN
6
7
A
16
DQ
15
DQ
6
DQ
12
DQ
10
DQ
1
OE#
A
0
8
GND
DQ
14
DQ
5
V
CC
DQ
11
DQ
2
DQ
8
GND
9
NC
DQ
7
DQ
13
DQ
4
DQ
3
DQ
9
DQ
0
CE#
NC
NC
NC
10
NC
11
NC
12
NC
A
15
A
12
A
9
RY/BY#
R
E
L
NC
C
D
E
F
A
19
A
7
A
4
A
1
P
G
H NC
NC
(FBGA060/048-P-0811)
-2-
A
R
Y
LH28F160BG-TL/BGH-TL
BLOCK ORGANIZATION
This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.
Boot Blocks :
The two boot blocks are intended to
replace a dedicated boot PROM in a micro-
processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the V
PP
, RP# and
WP# pins.
Parameter Blocks :
The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.
Main Blocks :
The reminder is divided into main
blocks for data or code storage. Each 16 M-bit
device contains thirty-one 32 k words (32 768
words) blocks.
DQ
0
-DQ
15
IM
MULTIPLEXER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y GATING
MAIN BLOCK 0
MAIN BLOCK 1
OUTPUT
BUFFER
IN
INPUT
BUFFER
I/O
LOGIC
REGISTER
BLOCK DIAGRAM
A
V
CC
COMMAND
USER
INTERFACE
OUTPUT
R
L
R
E
DATA
A
0
-A
19
INPUT
BUFFER
Y
DECODER
WRITE
STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
BOOT BLOCK 0
BOOT BLOCK 1
PARAMETER BLOCK 0
PARAMETER BLOCK 1
PARAMETER BLOCK 2
PARAMETER BLOCK 3
PARAMETER BLOCK 4
PARAMETER BLOCK 5
MAIN BLOCK 29
MAIN BLOCK 30
P
ADDRESS
LATCH
X
DECODER
31
32 k-WORD
MAIN BLOCKS
ADDRESS
COUNTER
-3-
Y
CE#
WE#
OE#
RP#
WP#
V
PP
RY/BY#
V
CC
GND
LH28F160BG-TL/BGH-TL
PIN DESCRIPTION
SYMBOL
A
0
-A
19
TYPE
INPUT
NAME AND FUNCTION
ADDRESS INPUTS :
Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS :
Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE :
Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN :
Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
RP#
INPUT
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. Block erase or word write with V
IH
<
OUTPUT ENABLE :
Gates the device’s outputs during a read cycle.
WRITE ENABLE :
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT :
Master control for boot blocks locking. When V
IL
, locked boot
blocks cannot be erased and programmed.
READY/BUSY :
Indicates the status of the internal WSM. When low, the WSM is
indicates that the WSM is ready for new commands, block erase is suspended, and
word write is inactive, word write is suspended, or the device is in deep power-down
mode.
BLOCK ERASE AND WORD WRITE POWER SUPPLY :
For erasing array blocks or
V
PP
SUPPLY
writing words. With V
PP
≤
V
PPLK
, memory contents cannot be altered. Block erase and
word write with an invalid V
PP
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce
spurious results and should not be attempted.
DEVICE POWER SUPPLY :
2.7 to 3.6 V. Do not float any power pins. With V
CC
≤
V
LKO
, all write attempts to the flash memory are inhibited. Device operations at invalid
V
CC
voltage (see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious results
and should not be attempted.
GROUND :
Do not float any ground pins.
NO CONNECT :
Lead is not internal connected; recommend to be floated.
DQ
0
-DQ
15
INPUT/
OUTPUT
OE#
WE#
WP#
INPUT
INPUT
INPUT
RY/BY#
OUTPUT
P
GND
NC
R
V
CC
SUPPLY
SUPPLY
E
L
IM
performing an internal operation (block erase or word write). RY/BY#-high-impedance
-4-
IN
A
RP# < V
HH
produce spurious results and should not be attempted.
R
Y
CE#
INPUT
LH28F160BG-TL/BGH-TL
1 INTRODUCTION
This datasheet contains LH28F160BG-TL/BGH-TL
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160BG-TL/
BGH-TL flash memories documentation also
includes ordering information which is referenced in
Section 7.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (3.0 V
V
CC
and V
PP
), independent of other blocks. Each
block can be independently erased 100 000 times.
Block erase suspend mode allows system software
to suspend block erase to read data from, or write
data to any other block.
Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 55 µs, 4 k-word blocks typically
within 60 µs (3.0 V V
CC
and V
PP
). Word write
suspend mode enables the system to read data
from, or write data to any other flash memory array
location.
The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see
Section 4.9
for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
V
IH
.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
1.1
New Features
Note following important differences :
• V
PPLK
has been lowered to 1.5 V to support
2.7 V block erase and word write operations.
Designs that switch V
PP
off during read
operations should make sure that the V
PP
voltage transitions to GND.
• To take advantage of Smart 3 technology, allow
V
PP
connection to 2.7 V or 12 V.
1.2
Product Overview
V
PP
at 2.7 V eliminates the need for a separate 12 V
converter, while V
PP
= 12 V maximizes block erase
and word write performance. In addition to flexible
unix/mpthreadport: Ensure enough thread stack to detect overflow.
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