ILX551A
2048-pixel CCD Linear Sensor (B/W)
For the availability of this product, please contact the sales office.
Description
The ILX551A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads B4 size documents at a density of
200DPI (Dot Per Inch). A built-in timing generator
and clock-drivers ensure direct drive at 5V logic for
easy use.
Features
•
Number of effective pixels: 2048 pixels
•
Pixel size: 14µm
×
14µm (14µm pitch)
•
Built-in timing generator and clock-drivers
•
Ultra low lag
V
DD2
NC
NC
NC
NC
V
DD2
φCLK
GND
V
DD2
SHSW
φROG
22 pin DIP (Cer-DIP)
Block Diagram
•
Maximum clock frequency: 5MHz
NC
10
Absolute Maximum Ratings
•
Supply voltage
•
Operating temperature
•
Storage temperature
Pin Configuration
(Top View)
V
DD1
V
DD2
11
6
–10 to +55
–30 to +80
V
V
°C
°C
GND
Read out gate
pulse generator
12
NC
13
Read out gate
CCD analog shift register
NC
14
Clock-drivers
Mode
selector
NC
15
NC
16
1
2
3
4
5
6
7
8
9
10
11
2048
1
Clock pulse generator
Sample-and-hold pulse generator
NC
NC
SHSW
φCLK
NC
NC
V
DD2
V
DD2
NC
φROG
21
V
DD2
GND
20
V
DD1
19
GND
18
NC
17
GND
16
NC
15
NC
14
NC
13
NC
12
GND
17
V
DD1
20
V
DD2
22
NC
18
Output amplifier
Sample-and-hold
circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
V
OUT
1
E00439-PS
2
3
6
7
8
5
D33
D15
D14
S1
V
OUT
22
V
DD2
19
21
4
11
9
S2048
S2047
D39
D38
D37
D36
D35
D34
S2
ILX551A
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
Symbol
V
OUT
NC
NC
SHSW
φCLK
NC
NC
V
DD2
V
DD2
NC
φROG
Description
Signal output
NC
NC
Switch
→
{
with S/HS/H GND
without
→
V
DD
2
Pin
No.
12
13
14
15
16
17
18
19
20
21
22
Symbol
GND
NC
NC
NC
NC
GND
NC
GND
V
DD1
V
DD2
V
DD2
GND
NC
NC
NC
NC
GND
NC
GND
Description
Clock pulse
NC
NC
5V power supply
5V power supply
NC
Clock pulse
9V power supply
5V power supply
5V power supply
Recommended Supply Voltage
Item
V
DD1
V
DD2
Min.
8.5
4.75
Typ.
9.0
5.0
Max.
9.5
5.25
Unit
V
V
Note)
Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise V
DD1
(9V) and then V
DD2
(5V).
To lower voltage, first lower V
DD2
(5V) and then V
DD1
(9V).
Mode Description
Mode in use
S/H
Yes
No
Pin condition
Pin 4 SHSW
GND
V
DD2
Input Capacity of Pins
Item
Input capacity of
φCLK
pin
Input capacity of
φROG
pin
Symbol
Cφ
CLK
Cφ
ROG
Min.
—
—
Typ.
10
10
Max.
—
—
Unit
pF
pF
Recommended Input Pulse Voltage
Item
Input clock high level
Input clock low level
Min.
4.5
0.0
Typ.
5.0
—
–2–
Max.
5.5
0.5
Unit
V
V
ILX551A
Electrooptical Characteristics
(Ta = 25°C, V
DD1
= 9V, V
DD2
= 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm))
Item
Secsitivity
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
9V supply current
5V supply current
Total transfer efficiency
Output impedance
Offset level
Symbol
R
PRNU
V
SAT
V
DRK
DSNU
IL
DR
SE
I
VDD1
I
VDD2
TTE
Z
O
V
OS
Min.
30
—
1.5
—
—
—
—
—
—
—
92.0
—
—
Typ.
40
2.0
1.8
0.3
0.5
0.02
6000
0.045
4.0
1.8
97.0
600
4.0
Max.
50
8.0
—
2.0
3.0
—
—
—
8.0
5.0
—
—
—
Unit
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
mA
%
Ω
V
Remarks
Note 1
Note 2
—
Note 3
Note 3
Note 4
Note 5
Note 6
—
—
—
—
Note 7
Notes)
1. For the sensitivity test light is applied with a uniform intensity of illumination.
2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU =
(V
MAX
– V
MIN
)/2
V
AVE
×
100 [%]
The maximum output is set to V
MAX
, the minimum output to V
MIN
and the average output to V
AVE
.
3. Integration time is 10ms.
4. V
OUT
= 500mV
5. DR =
V
SAT
V
DRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in
proportion to optical accumulated time.
6. SE =
V
SAT
R
7. Vos is defined as indicated below.
D31
OS
GND
,
D32
D33
S1
V
OS
–3–
Fig. 1. Clock Timing Diagram (without S/H mode)
5
φROG
0
2
3
4
2087
1
5
φCLK
0
1
D2
D3
D4
D5
D6
D11
D12
D13
D14
D15
D31
D32
D33
S1
S2
S3
S4
V
OUT
Optical black
(18 pixels)
Dummy signal (33 pixels)
Effective picture
elements signal
(2048 pixels)
1-line output period (2087 pixels)
S2045
S2046
S2047
S2048
D34
D35
D36
S37
S38
D39
Dummy signal
(6 pixels)
2
–4–
ILX551A
ILX551A
Fig. 2.
φCLK,
V
OUT
Timing
t1
t2
φCLK
t3
t4
,
,
,
,,
t5
V
OUT
t6
Item
φCLK
pulse rise/fall time
φCLK
pulse duty
∗
1
φCLK
– V
OUT
1
φCLK
– V
OUT
2
∗
1
100
×
t3/(t3 + t4)
Symbol
t1, t2
—
t5
t6
Min.
0
40
50
30
Typ.
10
50
80
75
Max.
—
60
110
120
Unit
ns
%
ns
ns
Fig. 3.
φROG, φCLK
Timing
φROG
t8
t9
t10
φCLK
t7
t11
Item
φROG, φCLK
pulse timing
φROG
pulse rise/fall time
φROG
pulse period
Symbol
t7, t11
t8, t10
t9
Min.
500
0
500
Typ.
1000
10
1000
–5–
Max.
—
—
—
Unit
ns
ns
ns
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