HIGH-SPEED 2.5V
70T3719/99M
256/128K x 72
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
◆
◆
◆
◆
◆
◆
◆
◆
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
Green parts available, see ordering information
Functional Block Diagram
BE
7L
BE
7R
BE
0L
BE
0R
FT/PIPE
L
1/0
0a 1a
a
0h 1h
h
1h 0h
h
1a 0a
a
1/0
FT/PIPE
R
R/W
L
R/W
R
CE
0L
CE
1L
1
0
1/0
B
W
0
L
B
W
7
L
B
W
7
R
B
W
0
R
1
0
1/0
CE
0R
CE
1R
OE
L
OE
R
D
OUT
0-8_L
D
OUT
9-17_L
D
OUT
18-26_L
D
OUT
27-35_L
D
OUT
36-44_L
D
OUT
45-53_L
D
OUT
54-62_L
D
OUT
63-72_L
1h 0h
1a 0a
a
h
D
OUT
0-8_R
D
OUT
9-17_R
D
OUT
18-26_R
D
OUT
27-35_R
D
OUT
36-44_R
D
OUT
45-53_R
D
OUT
54-62_R
D
OUT
63-72_R
0a 1a
h
a
0h 1h
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
256/128K x 72
MEMORY
ARRAY
Byte 0
I/O
0L
- I/O
71L
Byte 7
D
IN
_L
D
IN
_R
Byte 7
Byte 0
I/O
0R
- I/O
71R
CLK
L
A
17L
(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
17R
(1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0
R
REPEAT
R
ADS
R
CNTEN
R
CE
0L
CE
1L
R/W
L
COL
L
INT
L
ZZ
L
(2)
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0R
CE
1R
R/W
R
COL
R
INT
R
TDI
JTAG
TDO
TCK
T MS
T RST
LOGIC
NOTES:
1. Address A
17
is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
ZZ
R
(2)
5687 drw 01
NOVEMBER 2019
DSC 5687/6
1
©2019 Integrated Device Technology, Inc.
70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro-
nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3719/99M has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3719/99M can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (V
DD
) is at 2.5V.
6.42
2
70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(2,3,4,5)
70T3719/99M
BBG324
(6)
324-Pin BGA
Top View
(7)
06/27/05
1
I/O
39R
I/O
39L
I/O
40R
I/O
40L
I/O
47R
I/O
47L
I/O
48R
I/O
48L
I/O
55R
I/O
55L
I/O
56R
I/O
56L
I/O
63R
I/O
63L
I/O
64R
I/O
64L
I/O
71R
I/O
71L
1
2
I/O
38R
I/O
38L
I/O
41R
I/O
41L
I/O
46R
I/O
46L
I/O
49R
I/O
49L
I/O
54R
I/O
54L
I/O
57R
I/O
57L
I/O
62R
I/O
62L
I/O
65R
I/O
65L
I/O
70R
I/O
70L
2
3
I/O
37R
I/O
37L
I/O
42R
I/O
42L
I/O
45R
I/O
45L
I/O
50R
I/O
50L
I/O
53R
I/O
53L
I/O
58R
I/O
58L
I/O
61R
I/O
61L
I/O
66R
I/O
66L
I/O
69R
I/O
69L
3
4
I/O
36R
I/O
36L
I/O
43R
I/O
43L
5
COL
L
TDO
INT
L
TDI
6
A
15L
A
17L
(1)
A
16L
NC
V
DD
V
DD
7
A
12L
A
13L
A
11L
A
14L
V
DDQL
V
DDQL
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DDQL
V
DD
A
12R
A
13R
A
14R
A
15R
7
8
A
8L
A
10L
A
7L
A
9L
V
DDQR
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DDQL
V
DD
A
9R
A
7R
A
10R
A
11R
8
9
BE
7L
BE
6L
BE
0L
BE
4L
V
DDQR
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DD
BE
4R
BE
7R
BE
2R
A
8R
9
10
BE
2L
BE
5L
CE
0L
BE
3L
V
DDQL
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DDQL
CE
0R
BE
3R
BE
6R
BE
5R
10
11
CE
1L
BE
1L
12
ADS
L
OE
L
13
A
6L
REPEAT
L
14
A
1L
A
0L
A
3L
ZZ
L
OPT
L
V
DD
V
DDQR
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
OPT
R
A
1R
A
0R
A
3R
A
5R
14
15
I/O
32R
I/O
32L
I/O
31R
I/O
31L
I/O
24R
I/O
24L
I/O
23R
I/O
23L
I/O
16R
I/O
16L
I/O
15R
I/O
15L
I/O
8R
I/O
8L
I/O
7R
I/O
7L
I/O
0R
I/O
0L
15
16
I/O
33R
I/O
33L
I/O
30R
I/O
30L
I/O
25R
I/O
25L
I/O
22R
I/O
22L
I/O
17R
I/O
17L
I/O
14R
I/O
14L
I/O
9R
I/O
9L
I/O
6R
I/O
6L
I/O
1R
I/O
1L
16
17
I/O
34R
I/O
34L
I/O
29R
I/O
29L
I/O
26R
I/O
26L
I/O
21R
I/O
21L
I/O
18R
I/O
18L
I/O
13R
I/O
13L
I/O
10R
I/O
10L
I/O
5R
I/O
5L
I/O
2R
I/O
2L
17
18
I/O
35R
I/O
35L
I/O
28R
I/O
28L
I/O
27R
I/O
27L
I/O
20R
I/O
20L
I/O
19R
I/O
19L
I/O
12R
I/O
12L
I/O
11R
I/O
11L
I/O
4R
I/O
4L
I/O
3R
I/O
3L
18
5687 tbl 01
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
R/
W
L
CNTEN
L
CLK
L
V
DDQL
V
DD
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DD
V
DDQL
OE
R
CE
1R
BE
1R
BE
0R
11
A
5L
V
DDQR
V
DD
V
s s
V
s s
V
s s
V
s s
V
s s
V
s s
V
DDQR
V
DD
A
6R
ADS
R
A
4L
A
2L
V
DDQR
V
DD
V
DDQR
V
DDQL
V
s s
V
s s
V
s s
V
DDQL
V
DDQR
V
DD
A
2R
A
4R
I/O
44R
PL/
FT
L
I/O
44L
I/O
51R
I/O
51L
I/O
52R
I/O
52L
I/O
59R
I/O
59L
I/O
60R
I/O
60L
I/O
67R
V
DD
V
DDQR
V
DDQR
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQL
V
s s
V
s s
V
s s
V
DD
V
DDQR
V
DDQR
ZZ
R
COL
R
TMS
A
17R
(1)
I/O
67L
PL/
FT
R
A
16R
I/O
68R
I/O
68L
4
TCK
TRST
5
INT
R
NC
6
R/
W
R
REPEAT
R
CLK
R
CNTEN
R
12
13
NOTES:
1. Pin is a NC for IDT70T3799.
2. All V
DD
pins must be connected to 2.5V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 19mm x 19mm x 1.76mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
17L
(5)
I/O
0L
- I/O
71L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
BE
0L
-
BE
7L
V
DDQL
OPT
L
ZZ
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
INT
L
COL
L
INT
R
COL
R
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
17R
(5)
I/O
0R
- I/O
71R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
BE
0R
-
BE
7R
V
DDQR
OPT
R
ZZ
R
Names
Chip Enables (Input)
(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat
(3)
Byte Enables (9-bit bytes) (Input)
(6)
Power (I/O Bus) (3.3V or 2.5V)
(1)
(Input)
Option for selecting V
DDQX
(1,2)
(Input)
Sleep Mode pin
(4)
(Input)
Power (2.5V)
(1)
(Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
5687 tbl 02
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to V
DD
(2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to V
SS
(0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundary scan not be operated during sleep mode.
5. Address A
17x
is a NC for the IDT70T3799M.
6. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH
, i.e., the
signals take two cycles to deselect.
6.42
4
70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
OE
X
X
X
X
X
X
X
L
L
L
L
H
X
CLK
X
X
CE
0
H
X
L
L
L
L
L
L
L
L
L
X
X
CE
1
X
L
H
H
H
H
H
H
H
H
H
X
X
Byte Enables
All
BE
= X
All
BE
= X
All
BE
= H
BE
n
= L, All other
BE
= H
BE
4-7
= L,
BE
0-3
= H
BE
4-7
= H,
BE
0-3
= L
BE
0-7
= L
BE
n
= L, All other
BE
= H
BE
4-7
= L,
BE
0-3
= H
BE
4-7
= H,
BE
0-3
= L
All
BE
= L
All
BE
= X
All
BE
= X
R/W
X
X
X
L
L
L
L
H
H
H
H
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
H
(1,2,3,4,5)
MODE
Deselected: Power Down
Deselected: Power Down
All Bytes Deselected
I/O Operation
(6)
All Bytes= High-Z
All Bytes = High-Z
All Bytes = High-Z
Byte
n
= D
IN
, All other Bytes = High-Z Write to Byte X Only
Byte
4-7
= D
IN
, Byte
0-3
= High-Z
Byte
4-7
= High-Z, Byte
0-3
= D
IN
Byte
0-7
= D
IN
Write to Lower Bytes Only
Write to Upper Bytes Only
Write to All Bytes
Byte
n
= D
OUT
, All other Bytes = High-Z Read Byte X Only
Byte
4-7
= D
OUT
, Byte
0-3
= High-Z
Byte
4-7
= High-Z, Byte
0-3
= D
OUT
All Bytes = D
OUT
All Bytes = High-Z
All Bytes = High-Z
Read Lower Bytes Only
Read Upper Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
5687 tbl 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, REPEAT
= X.
3.
OE
and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5. For the examples shown here,
BEn
may correspond to any of the eight byte enable signals.
Truth Table II—Address Counter Control
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
An
CLK
ADS
(4)
L
H
H
X
CNTEN
X
L
(5)
H
X
REPEAT
(4,6)
H
H
H
L
(1,2)
I/O
(3)
D
I/O
(n)
External Address Used
MODE
D
I/O
(n+1)
Counter Enabled-Internal Address generation
D
I/O
(n+1)
Enabled Address Blocked-Counter disabled (An + 1 reused)
D
I/O
(n)
Counter Set to last valid
ADS
load
5687 tbl 04
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W,
CE
0
, CE
1
,
BEn
and
OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
BEn.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
BEn.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS.
This value is not set at power-up: a known location should be loaded
via
ADS
during initialization if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
6.42
5
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